What's Changed

• Fixing selecting the module and reflecting the respective signal table by @aneriach in #612
• Cloning and matching by @mkorbel1 in #614
• Preparing to release v0.6.6 by @mkorbel1 in #618

New Contributors

• @aneriach made their first contribution in #612

Full Changelog: v0.6.5...v0.6.6

What's Changed

• bug fix for zero value toRadixString() by @desmonddak in #606
• Preparing to release v0.6.5 by @mkorbel1 in #607

Full Changelog: v0.6.4...v0.6.5

What's Changed

• Fix bug in LogicStructure.previousValue by @mkorbel1 in #565
• Deprecate Port and move to Logic.port for API consistency by @lucasphillips in #575
• Add documentation and example code for selectIndex and selectFrom by @laeticiachee in #576
• Fix bug in cross-stage accesses in Pipeline by @mkorbel1 in #588
• Enhance LogicValue.toRadixString to enable fixed-width output by @desmonddak in #583
• FiniteStateMachine upgrades by @mkorbel1 in #593
• Modularity and improvements for Synth infrastructure by @mkorbel1 in #598
• Fix memory leak in combinational guarding by @mkorbel1 in #602
• Preparing to release v0.6.4 by @mkorbel1 in #603

New Contributors

• @lucasphillips made their first contribution in #575
• @laeticiachee made their first contribution in #576

Full Changelog: v0.6.3...v0.6.4

What's Changed

• Bug fix for withSet in LogicStructure. by @kimmeljo in #561
• Fix bug where non-async flop generates async flop by @mkorbel1 in #564
• Rohd Devtools Extension Refactor to BLoC by @robtorx in #562
• Preparing to release v0.6.3 by @mkorbel1 in #563

New Contributors

• @robtorx made their first contribution in #562

Full Changelog: v0.6.2...v0.6.3

What's Changed

• Transition to using a different addition syntax for lint avoidance by @mkorbel1 in #478
• Simulator end of sim actions and exception handling by @mkorbel1 in #558
• Support VCDs generated by Verilator in VcdParser by @mkorbel1 in #557
• Preparing to release v0.6.2 by @mkorbel1 in #560

Full Changelog: v0.6.1...v0.6.2

What's Changed

• Fix bug in SSA discovery when LogicStructures are used by @mkorbel1 in #540
• Fix bug where Module.build didn't follow through structs containing ports properly, plus improved debug messaging. by @mkorbel1 in #541
• fix radix10 issue in toRadixString by @desmonddak in #543
• Add Logic.named and broaden clone by @mkorbel1 in #550
• Preparing to release v0.6.1 by @mkorbel1 in #555

Full Changelog: v0.6.0...v0.6.1

What's Changed

• LogicNets, inOuts, and TriStateBuffer (support for bidirectional wires) by @mkorbel1 in #485
• Improve simulator timestamp in past errors, suggest reset, fix #490 by @mkorbel1 in #491
• RTL to have one array-array assignment instead of bit blasted assignments by @sshankar4 in #487
• Performance fixes: wrong collections and unmodifiable views causing inefficiencies by @mkorbel1 in #492
• Update analysis options, lint cleanup, SDK workaround removal by @mkorbel1 in #495
• Fix bug in internal array discovery during Module build by @mkorbel1 in #494
• Fix bug where unconnected array drivers may be omitted incorrectly by @mkorbel1 in #496
• Add support for SystemVerilog parameter passthroughs by @mkorbel1 in #497
• Do not generate SystemVerilog parameter syntax when there are 0 parameters by @mkorbel1 in #498
• Fix bug in LogicStructure.getRange calculations by @mkorbel1 in #499
• Logic.assignSubset for partial assignments to Logic by @mkorbel1 in #502
• Add inputSource and inOutSource to Module by @mkorbel1 in #503
• Bug fix: shuffled array assignments incorrectly collapsed in generated SV by @mkorbel1 in #504
• Upgrade and improve Uniquifier API by @mkorbel1 in #505
• Improved port already exists error message with module name by @c0d3-br3ak9r in #526
• Doc fixes and a couple more tests by @mkorbel1 in #525
• RadixString code by @desmonddak in #529
• Allow LogicNets to bidirectionally drive operations which are just wires by @mkorbel1 in #532
• Async Reset Improvements by @mkorbel1 in #533
• Fix bugs in Simulator error handling and end of simulation by @mkorbel1 in #515
• LogicValue radixString uses underscore separators by default by @desmonddak in #535
• Improvements to asynchronous trigger and injection handling by @mkorbel1 in #537
• Documentation and miscellaneous minor cleanup by @mkorbel1 in #538
• Preparing to release v0.6.0 by @mkorbel1 in #539

New Contributors

• @sshankar4 made their first contribution in #487
• @c0d3-br3ak9r made their first contribution in #526
• @desmonddak made their first contribution in #529

Full Changelog: v0.5.3...v0.6.0

What's Changed

• Absolute value by @dmetis in #442
• Make conditional assign a little more optimistic with invalid values by @mkorbel1 in #459
• Add youtube channel link to Readme.md by @quekyj in #460
• ROHD Module Hierarchy and Signals Visualization (Flutter UI) by @quekyj in #435
• Update analysis options and doc checks for Dart 3.3.0 by @mkorbel1 in #463
• Fix documentation generation by @mkorbel1 in #467
• Simulator upgrades for rohme compatibility (registering now and cancelling) by @AdamRose66 in #468
• Issue #377: assign a logic subset to logic (array) by @RPG-coder-intc in #456
• Fix a bug where array port element naming collisions with port names caused misconnections by @mkorbel1 in #473
• chore(devtool): build devtool artifact and commit to other branch by @quekyj in #461
• fix: update flutter version to the latest by @quekyj in #474
• Refactored tick() in simulator.dart by @AdamRose66 in #475
• Update to use new runners in github actions by @mkorbel1 in #417
• Adjust CI timeout and runners by @mkorbel1 in #480

New Contributors

• @AdamRose66 made their first contribution in #468

Full Changelog: v0.5.2...v0.5.3

What's Changed

• Allow constant Z driving to show up in SV without error by @mkorbel1 in #441
• Logic value test improvement and minor fixes by @mjayasim9 in #422
• Optimize performance of Combinational.ssa driver search by @mkorbel1 in #443
• Support compiling ROHD to JavaScript by @mkorbel1 in #445
• Get a Logic of a Logic List via an index by @RPG-coder-intc in #438
• Pipeline fixes and improvements by @mkorbel1 in #447
• Update counter example to be simpler and a better reference by @mkorbel1 in #448
• Update default permissions in GH actions by @mkorbel1 in #452
• Update some pages of the user guide by @mkorbel1 in #453
• Fix defaultNextState diagram generation in FSM by @mkorbel1 in #454
• Make Simulator.endSimulation return a Future by @mkorbel1 in #455
• Fix bugs in LogicStructure instrumentation calls to packed and changed issues across Simulator.reset by @mkorbel1 in #458

Full Changelog: v0.5.1...v0.5.2

What's Changed

• Sort ports and internal signals, fix #395 by @mkorbel1 in #420
• Allow multiple nonblocking assignments, fix #321 by @mkorbel1 in #421
• Fix bug where generated SV has lint issues with plus and shift-left due to SV width expansion by @mkorbel1 in #423
• Signal naming improvements by @mkorbel1 in #439
• More module and signal naming improvements by @mkorbel1 in #440

Full Changelog: v0.5.0...v0.5.1