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Fix bug in SSA discovery when LogicStructures are used #540

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Jan 9, 2025
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16 changes: 15 additions & 1 deletion lib/src/modules/conditionals/combinational.dart
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
// Copyright (C) 2021-2024 Intel Corporation
// Copyright (C) 2021-2025 Intel Corporation
// SPDX-License-Identifier: BSD-3-Clause
//
// combinational.dart
Expand Down Expand Up @@ -137,6 +137,20 @@ class Combinational extends Always {
} else {
toParse.addAll(tpi.dstConnections);
}

// This is critical to make sure we are notifying downstream SSA's even
// if they are driven as a result of being a part of a modified structure.
if (tpi.parentStructure != null) {
toParse.add(tpi.parentStructure!);
}

// This is probably unnecessary, as the SSA would not allow someone to
// reference an element of a structure without separately SSA'ing it.
// However, leaving this in here just in case (probably negligible perf
// impact).
if (tpi is LogicStructure) {
toParse.addAll(tpi.elements);
}
}
}

Expand Down
4 changes: 2 additions & 2 deletions test/pipeline_test.dart
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
// Copyright (C) 2021-2024 Intel Corporation
// Copyright (C) 2021-2025 Intel Corporation
// SPDX-License-Identifier: BSD-3-Clause
//
// pipeline_test.dart
Expand Down Expand Up @@ -247,7 +247,7 @@ void main() {
throwsRangeError);
});

test('getting unregisterd signal on pipeline is error', () {
test('getting unregistered signal on pipeline is error', () {
expect(
() => Pipeline(Logic(), signals: [
Logic()
Expand Down
88 changes: 87 additions & 1 deletion test/ssa_test.dart
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
// Copyright (C) 2023 Intel Corporation
// Copyright (C) 2023-2025 Intel Corporation
// SPDX-License-Identifier: BSD-3-Clause
//
// ssa_test.dart
Expand All @@ -21,6 +21,90 @@ abstract class SsaTestModule extends Module {
int model(int a);
}

class SimpleStruct extends LogicStructure {
SimpleStruct()
: super([Logic(width: 4), Logic(width: 4)], name: 'simple_struct');
}

class StructOpRepack extends Module {
late final SimpleStruct x = SimpleStruct()..gets(output('x'));

StructOpRepack(SimpleStruct a) {
a = SimpleStruct()..gets(addInput('a', a, width: 8));
final x_ = SimpleStruct();

x_.elements[0] <= a.elements[0] + 1;
x_.elements[1] <= a.elements[1] + 2;

addOutput('x', width: 8) <= x_;
}
}

class SsaModWithStructElements extends SsaTestModule {
SsaModWithStructElements(Logic a) : super(name: 'struct_elements') {
a = addInput('a', a, width: 8);
final x = addOutput('x', width: 8);

final s1 = SimpleStruct();

final sx = SimpleStruct();

Combinational.ssa((s) => [
s(s1) < a,
s(sx) < StructOpRepack(SimpleStruct()..gets(s(s1))).x,
]);

x <= sx;
}

@override
int model(int a) {
final orig = LogicValue.ofInt(a, 8);
return [
orig.getRange(0, 4) + 1,
orig.getRange(4, 8) + 2,
].rswizzle().toInt();
}
}

class StructOpSplit extends Module {
Logic get x0 => output('x0');
Logic get x1 => output('x1');

StructOpSplit(SimpleStruct a) {
a = SimpleStruct()..gets(addInput('a', a, width: 8));
final x0 = addOutput('x0', width: 4);
final x1 = addOutput('x1', width: 4);

x0 <= a.elements[0] + 1;
x1 <= a.elements[1] + 2;
}
}

class SsaModWithStructSplit extends SsaTestModule {
SsaModWithStructSplit(Logic a) : super(name: 'struct_split') {
a = addInput('a', a, width: 8);
final x = addOutput('x', width: 8);

final s1 = SimpleStruct();

Combinational.ssa((s) => [
s(s1) < a,
s(x) <
() {
final splitMod = StructOpSplit(SimpleStruct()..gets(s(s1)));
return (splitMod.x0 + splitMod.x1).zeroExtend(8);
}(),
]);
}

@override
int model(int a) {
final orig = LogicValue.ofInt(a, 8);
return (orig.getRange(0, 4) + 1 + orig.getRange(4, 8) + 2).toInt();
}
}

class SsaModAssignsOnly extends SsaTestModule {
SsaModAssignsOnly(Logic a) : super(name: 'assigns_only') {
a = addInput('a', a, width: 8);
Expand Down Expand Up @@ -338,6 +422,8 @@ void main() {
SsaMix(aInput),
SsaNested(aInput),
SsaMultiDep(aInput),
SsaModWithStructElements(aInput),
SsaModWithStructSplit(aInput),
];

for (final mod in mods) {
Expand Down