Implement FF in IO blocks. #298
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There are three registers in IO blocks: IREG, OREG, and TREG. Not in all of them, but only where there is IOLOGIC because these registers are part of it. Hence the first limitation: if FF is placed in an IO block, the rest of the IOLOGIC cannot be used. The second limitation is related to the fact that all three registers have common wires CLK, ClockEnable and LocalSetReset and this dictates the types of flipflop's - let's say DFF (in Gowin's implementation) requires a constant connection CE to VCC, so you can not use in the same IO block DFFE, which CE is a signal. Signed-off-by: YRabbit <[email protected]>
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Isn't OREG a subset of ODDR/OSER modes? |
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Maybe at the lowest level Gowin borrows some transistors from ODDR/OSER to make this flipflop, but I have strong doubts about that - there aren't enough IO blocks for this saving to make any difference. So I think it's a normal separate register whose output is connected to MUX, which by the way doesn't allow to use any other iologic if OREG is used :)
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There are three registers in IO blocks: IREG, OREG, and TREG. Not in all of them, but only where there is IOLOGIC because these registers are part of it.
Hence the first limitation: if FF is placed in an IO block, the rest of the IOLOGIC cannot be used.
The second limitation is related to the fact that all three registers have common wires CLK, ClockEnable and LocalSetReset and this dictates the types of flipflop's - let's say DFF (in Gowin's implementation) requires a constant connection CE to VCC, so you can not use in the same IO block DFFE, which CE is a signal.