drivers: flash: flash_mcux_flexspi: add support for W25Q512JV #80261
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| @@ -886,6 +886,37 @@ static int flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data *data, | |||
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| /* Switch on manufacturer and vendor ID */ | |||
| switch (vendor_id & 0xFFFF) { | |||
| case 0x40ef: | |||
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not going to request changes to this PR about this right now since it's a bug fix and what im gonna ask about is more than a minor tweak... , but this doesn't seem scalable here, we dont really want all this code for many different flash chips in the image, do we ? and do we expect the flexspi hardware connection to change dynamically (runtime) ? ie, why isnt these luts somehow determined statically
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No, it isn't scalable at all. The SFDP driver design was initially intended to save us from statically defined LUTs, but most flash chips that support 4 byte addressing do it via a "vendor defined command set"- so for example, this W25Q512JV worked fine with 3 byte addressing, but that doesn't let you access all 64 MB of the flash chip, hence the need for this switch case.
Long term the solution is to move the FlexSPI under the MSPI API, so we can just write MSPI drivers for all these flash chips.
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SFDP has codes for standard instructions but JESD216 but mentions that vendors often chosen to extend set of instructions; there is table of instructions that support 4 byte addressin, but in this case this is standard 0xec Fast Read 1s-4s-4s.
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I'm not sure I follow. Does JESD216 define a DWORD that can be read to determine if the flash uses standard 4 byte addressing instructions (IE 0xEC)? I could not find one in the standard.
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I have jesd216.F from 2022, and there is chapter: 6.7 "JEDEC 4-byte Address Instruction Parameter Header and Table", p67.
You can also search for "Support for (1S-1S-4S) Page Program Command, Instruction=34h"
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But I think that since you have already limited the setup to specific vendor/memory, there is no need to query and you can just enforce directly what you want.
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I have jesd216.F from 2022, and there is chapter: 6.7 "JEDEC 4-byte Address Instruction Parameter Header and Table", p67.
You can also search for "Support for (1S-1S-4S) Page Program Command, Instruction=34h"
Yup, you are right- this is the proper way to do this. I agree that for now this approach is ok, but this is how we should handle SFDP probes for QSPI flash in the future I think.
Add support for the W25Q512JV with the FLEXSPI, using a custom LUT table. Signed-off-by: Daniel DeGrasse <[email protected]>
WS25Q512JV can only run at 104MHz at 3.3V, unless the read parameter bits are changed. Since we don't reprogram these currently, reduce max frequency to safe value Signed-off-by: Daniel DeGrasse <[email protected]>
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@de-nordic could you take a look at this PR? |
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@danieldegrasse Looks OK to me, but I can only verify characteristics of the memory, to my understanding, datasheet and JESD216.
The ownership here is on NXP platform maintainers, I am only in control of API.
(btw, we need to figure out to stop doing SoC vendor specific SPI memory device drivers)
Strongly agree- I want to move this to use the MSPI API in the (hopefully) near term. |
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Add support for the W25Q512JV with the FLEXSPI, using a custom LUT table.