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@ycsin ycsin commented Sep 27, 2024

Made by @dreiss in our internal fork:

Restore the s0 we saved early in ISR entry so it shows up properly in the CSF.

Fixes #79298

Restore the s0 we saved early in ISR entry so it shows up
properly in the CSF.

Signed-off-by: David Reiss <[email protected]>
Signed-off-by: Yong Cong Sin <[email protected]>
Test if callee-saved-registers values are as expected.

Signed-off-by: David Reiss <[email protected]>
Signed-off-by: Yong Cong Sin <[email protected]>
@ycsin ycsin marked this pull request as ready for review September 28, 2024 01:59
@zephyrbot zephyrbot added the area: RISCV RISCV Architecture (32-bit & 64-bit) label Sep 28, 2024
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Good catch.

@aescolar aescolar merged commit 4da4ee8 into zephyrproject-rtos:main Oct 2, 2024
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@ycsin ycsin added the backport v3.7-branch Request backport to the v3.7-branch label Oct 2, 2024
@ycsin ycsin deleted the pr/riscv-csf-test branch October 2, 2024 08:22
@ycsin ycsin linked an issue Oct 2, 2024 that may be closed by this pull request
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area: RISCV RISCV Architecture (32-bit & 64-bit) backport v3.7-branch Request backport to the v3.7-branch
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arch: riscv: the s0 dumped during a fatal error is not correct
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