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Add support eDMA for S32K344 #61311
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Add support eDMA for S32K344 #61311
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The following west manifest projects have been modified in this Pull Request:
Note: This message is automatically posted and updated by the Manifest GitHub Action. |
@Dat-NguyenDuy, please take a look at the CI failures. |
drivers/dma/dma_mcux_edma.c
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#define DEV_DMAMUX_BASE(dev, idx) ((DMAMUX_Type *)DEV_CFG(dev)->dmamux_base[idx]) | ||
#define DEV_DMAMUX_IDX(dev, ch) (ch / DEV_CFG(dev)->channels_per_mux) | ||
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#ifdef CONFIG_SOC_SERIES_S32K3_M7 |
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Is there a reason this code needs to be SOC dependent?
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This is SoC dependency, i'm considering it's worth to add a dt properties for it
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I'd suggest to add a binding property to remove the SoC dependency in the driver, e.g.
#define DEV_DMAMUX_CHANNEL(dev, ch) ((ch % DEV_CFG(dev)->channels_per_mux) ^ (DEV_CFG(dev)->mux_channel_mask))
and use a default of 0
which would be the logical way to access the DMA CHCFGn
registers. The SoCs that have a different arrangement can change the mux-channel-mask
(feel free to suggest a better name) as needed, like in the case of K344 to 3
.
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I've updated
drivers/dma/dma_mcux_edma.c
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IRQ_CONFIG(n, 16, dma_mcux_edma_error_irq_handler); \ | ||
\ | ||
LOG_DBG("install irq done"); \ | ||
#ifdef CONFIG_DMA_MCUX_SINGLE_IRQ_PER_CHANNEL |
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It seems like this macro will install an interrupt handler per each channel of the EDMA. Existing NXP SOCs using the legacy EDMA also have a per channel interrupt, but have a combined error interrupt. Would it be possible to enable per channel interrupts for all EDMA instances, and only enable the error interrupt servicing in the channel interrupt when this Kconfig was set?
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Good idea, it's possible, i just re-pushed the update
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@danieldegrasse could you pls revisit if this one looks fine to you
regression test done. no issues found. |
Minor update |
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Test PASS on NXP regression for RT series
@Dat-NguyenDuy , thank you for the PR. Overall this looks great. My request would be not leave the current EDMA driver Kconfigs and device tree binding names unchanged to maintain backwards compatibility. |
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Request to leave the EDMA Kconfigs and device tree binding names unchanged.
@mmahadevan108 I'm a bit puzzled, I had the impression we agreed naming existing binding v2 and the new one v3 to follow the corresponding DMA versions (#61311 (comment)). We should add this to release notes to make sure the changes are visible to users. |
Add new dt binding for edma v3 that inherits whole dt properties from current version. One more property is added for SoCs that don't have separate error interrupt id, use same id with channel interrupt Signed-off-by: Dat Nguyen Duy <[email protected]>
On S32K344, the offset in memory map between each channel is 0x4000 for most channels, but there is specific case is between channel 11 and 12 which is 0x1D4000 instead. As a consequence, 32 channels are divided to two parts: one starts from channel 0 -> 11. The other is from channel 128 to 145. The channel gap is from 12 -> 127. For user and data structures in shim driver, the channel's value comes from 0 --> 31. Above constraint will be counted when interact with the mcux sdk Beside that, the DMAMUX register in this platform is very specific, not in identical with DMAMUX channel, so shim driver is updated to cover this case Signed-off-by: Dat Nguyen Duy <[email protected]>
dc50609
I re-pushed to leave current EDMA Kconfig and dts binding |
Please update |
Enable dma support for mr_canhubk3 board Signed-off-by: Dat Nguyen Duy <[email protected]>
Add devicetree overlay for enabling dma test for mr_canhubk3 board Signed-off-by: Dat Nguyen Duy <[email protected]>
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@manuargue , the general guidance from the Zephyr project is to limit breaking backward compatibility as much as possible. In this case, we are sticking with the SDMA naming convention for the driver folders. |
regression test is done. no issue found in rt platforms with this change |
This extends NXP current eDMA shim driver for supporting eDMA v3 on S32K344