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Update core Espressif wolfcrypt port #9242

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18 changes: 18 additions & 0 deletions .wolfssl_known_macro_extras
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Original file line number Diff line number Diff line change
Expand Up @@ -43,6 +43,12 @@ BSP_SDCARD_SDHC_CHANNEL
BSP_SDCARD_SPI_CHANNEL
CAAM_OUT_INVALIDATE
CERT_REL_PREFIX
CHIP_FEATURE_BLE
CHIP_FEATURE_BT
CHIP_FEATURE_EMB_FLASH
CHIP_FEATURE_EMB_PSRAM
CHIP_FEATURE_IEEE802154
CHIP_FEATURE_WIFI_BGN
CIOCASYMFEAT
CIOCGSESSINFO
CMSIS_OS2_H_
Expand Down Expand Up @@ -103,16 +109,23 @@ CONFIG_ESP_WOLFSSL_NO_HW_RSA_PRI_EXPTMOD
CONFIG_ESP_WOLFSSL_NO_HW_RSA_PRI_MP_MUL
CONFIG_ESP_WOLFSSL_NO_HW_RSA_PRI_MULMOD
CONFIG_ESP_WOLFSSL_NO_STACK_SIZE_BUILD_WARNING
CONFIG_ESP_WOLFSSL_USE_RSA
CONFIG_FREERTOS_HZ
CONFIG_FREERTOS_UNICORE
CONFIG_FREERTOS_USE_TRACE_FACILITY
CONFIG_IDF_INIT_VERSION
CONFIG_IDF_TARGET
CONFIG_IDF_TARGET_ARCH_RISCV
CONFIG_IDF_TARGET_ARCH_XTENSA
CONFIG_IDF_TARGET_ESP32
CONFIG_IDF_TARGET_ESP32C2
CONFIG_IDF_TARGET_ESP32C3
CONFIG_IDF_TARGET_ESP32C5
CONFIG_IDF_TARGET_ESP32C6
CONFIG_IDF_TARGET_ESP32C61
CONFIG_IDF_TARGET_ESP32H2
CONFIG_IDF_TARGET_ESP32H21
CONFIG_IDF_TARGET_ESP32H4
CONFIG_IDF_TARGET_ESP32P4
CONFIG_IDF_TARGET_ESP32S2
CONFIG_IDF_TARGET_ESP32S3
Expand Down Expand Up @@ -174,6 +187,7 @@ CONFIG_WOLFSSL_TARGET_PORT
CONFIG_WOLFSSL_TLS13_ENABLED
CONFIG_WOLFSSL_TLS_VERSION_1_2
CONFIG_WOLFSSL_TLS_VERSION_1_3
CONFIG_WOLFSSL_USE_MY_PRIVATE_CONFIG
CONFIG_WOLFTPM
CONFIG_WOLFTPM_EXAMPLE_NAME_ESPRESSIF
CONFIG_X86
Expand Down Expand Up @@ -275,6 +289,7 @@ HAVE_MDK_RTX
HAVE_NETX_BSD
HAVE_PKCS7_RSA_RAW_SIGN_CALLBACK
HAVE_POCO_LIB
HAVE_RSA
HAVE_RTP_SYS
HAVE_SECURE_GETENV
HAVE_STACK_SIZE_VERBOSE_LOG
Expand Down Expand Up @@ -310,6 +325,8 @@ LIBWOLFSSL_VERSION_GIT_HASH_DATE
LIBWOLFSSL_VERSION_GIT_ORIGIN
LIBWOLFSSL_VERSION_GIT_SHORT_HASH
LIBWOLFSSL_VERSION_GIT_TAG
LIBWOLFSSL_VERSION_IDF_PATH
LIBWOLFSSL_VERSION_WOLFSSL_ROOT
LINUXKM_DONT_FORCE_FIPS_ENABLED
LINUXKM_LKCAPI_PRIORITY_ALLOW_MASKING
LINUX_CYCLE_COUNT
Expand Down Expand Up @@ -725,6 +742,7 @@ WOLFSSL_HARDEN_TLS_ALLOW_OLD_TLS
WOLFSSL_HARDEN_TLS_ALLOW_TRUNCATED_HMAC
WOLFSSL_HARDEN_TLS_NO_PKEY_CHECK
WOLFSSL_HARDEN_TLS_NO_SCR_CHECK
WOLFSSL_HAVE_LINKER_REGION_PEEK
WOLFSSL_HOSTNAME_VERIFY_ALT_NAME_ONLY
WOLFSSL_I2D_ECDSA_SIG_ALLOC
WOLFSSL_IAR_ARM_TIME
Expand Down
15 changes: 10 additions & 5 deletions wolfcrypt/benchmark/benchmark.c
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Original file line number Diff line number Diff line change
Expand Up @@ -380,7 +380,8 @@
.resolution_hz = CONFIG_XTAL_FREQ * 100000,
};
#elif defined(CONFIG_IDF_TARGET_ESP32C3) || \
defined(CONFIG_IDF_TARGET_ESP32C6)
defined(CONFIG_IDF_TARGET_ESP32C6) || \
defined(CONFIG_IDF_TARGET_ESP32C61)
#include <esp_cpu.h>
#if ESP_IDF_VERSION_MAJOR >= 5
#include <driver/gptimer.h>
Expand Down Expand Up @@ -1494,7 +1495,8 @@ static const char* bench_result_words3[][5] = {
#endif
#if defined(CONFIG_IDF_TARGET_ESP32C2) || \
defined(CONFIG_IDF_TARGET_ESP32C3) || \
defined(CONFIG_IDF_TARGET_ESP32C6)
defined(CONFIG_IDF_TARGET_ESP32C6) || \
defined(CONFIG_IDF_TARGET_ESP32C61)

#ifdef WOLFSSL_BENCHMARK_TIMER_DEBUG
ESP_ERROR_CHECK(gptimer_get_raw_count(esp_gptimer, &thisTimerVal));
Expand Down Expand Up @@ -1651,7 +1653,8 @@ static const char* bench_result_words3[][5] = {
* for the next measurement. */
#if defined(CONFIG_IDF_TARGET_ESP32C2) || \
defined(CONFIG_IDF_TARGET_ESP32C3) || \
defined(CONFIG_IDF_TARGET_ESP32C6)
defined(CONFIG_IDF_TARGET_ESP32C6) || \
defined(CONFIG_IDF_TARGET_ESP32C61)
{
#ifdef WOLFSSL_BENCHMARK_TIMER_DEBUG
ESP_ERROR_CHECK(gptimer_get_raw_count(esp_gptimer,
Expand Down Expand Up @@ -15664,7 +15667,8 @@ int wolfcrypt_benchmark_main(int argc, char** argv)
{
#if defined(CONFIG_IDF_TARGET_ESP32C2) || \
defined(CONFIG_IDF_TARGET_ESP32C3) || \
defined(CONFIG_IDF_TARGET_ESP32C6)
defined(CONFIG_IDF_TARGET_ESP32C6) || \
defined(CONFIG_IDF_TARGET_ESP32C61)
{
#ifdef WOLFSSL_BENCHMARK_TIMER_DEBUG
if (esp_gptimer == NULL) {
Expand All @@ -15687,7 +15691,8 @@ int wolfcrypt_benchmark_main(int argc, char** argv)

#if defined(CONFIG_IDF_TARGET_ESP32C2) || \
defined(CONFIG_IDF_TARGET_ESP32C3) || \
defined(CONFIG_IDF_TARGET_ESP32C6)
defined(CONFIG_IDF_TARGET_ESP32C6) || \
defined(CONFIG_IDF_TARGET_ESP32C61)
{
#ifdef WOLFSSL_BENCHMARK_TIMER_DEBUG
ESP_ERROR_CHECK(gptimer_stop(esp_gptimer));
Expand Down
9 changes: 5 additions & 4 deletions wolfcrypt/src/port/Espressif/esp32_aes.c
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Original file line number Diff line number Diff line change
Expand Up @@ -115,7 +115,8 @@ static int esp_aes_hw_InUse(void)
DPORT_REG_WRITE(AES_DMA_ENABLE_REG, 0);
}
#elif defined(CONFIG_IDF_TARGET_ESP32C3) || \
defined(CONFIG_IDF_TARGET_ESP32C6)
defined(CONFIG_IDF_TARGET_ESP32C6) || \
defined(CONFIG_IDF_TARGET_ESP32C61)
{
/* Select working mode. Can be typical or DMA.
* 0 => typical
Expand Down Expand Up @@ -216,7 +217,7 @@ static int esp_aes_hw_Set_KeyMode(Aes *ctx, ESP32_AESPROCESS mode)
ESP_LOGE(TAG, "esp_aes_hw_Set_KeyMode unsupported mode: %i", mode_);
ret = BAD_FUNC_ARG;
}
#elif defined(CONFIG_IDF_TARGET_ESP32C6)
#elif defined(CONFIG_IDF_TARGET_ESP32C6) || defined(CONFIG_IDF_TARGET_ESP32C61)
#define TARGET_AES_KEY_BASE AES_KEY_0_REG
if (mode_ == 1 || mode_ == 3 || mode_ == 5 || mode_ > 6) {
/* this should have been detected in aes.c and fall back to SW */
Expand Down Expand Up @@ -303,7 +304,7 @@ static void esp_aes_bk(const byte* in, byte* out)

/* read-out blocks */
esp_dport_access_read_buffer((uint32_t*)outwords, AES_TEXT_OUT_BASE, 4);
#elif defined(CONFIG_IDF_TARGET_ESP32C6)
#elif defined(CONFIG_IDF_TARGET_ESP32C6) || defined(CONFIG_IDF_TARGET_ESP32C61)
/* See ESP32-C6 technical reference manual:
** 18.4.3 Operation process using CPU working mode.
** The ESP32-C6 also supports a DMA mode. (not ywt implemented)
Expand Down Expand Up @@ -380,7 +381,7 @@ int wc_esp32AesSupportedKeyLenValue(int keylen)
ret = ESP_OK; /* keylen 24 (192 bit) not supported */
}

#elif defined(CONFIG_IDF_TARGET_ESP32C6)
#elif defined(CONFIG_IDF_TARGET_ESP32C6) || defined(CONFIG_IDF_TARGET_ESP32C61)
if (keylen == 16 || keylen == 32) {
ret = 1;
}
Expand Down
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