wolfSSL · dpalffy · Mar 31, 2023 · Mar 31, 2023 · Mar 31, 2023 · Mar 31, 2023
diff --git a/IDE/Espressif/ESP-IDF/README_32se.md b/IDE/Espressif/ESP-IDF/README_32se.md
@@ -15,11 +15,10 @@ Including the following examples:
 2. Microchip CryptoAuthentication Library: https://github.com/MicrochipTech/cryptoauthlib
 
 ## Setup
-1. Comment out `#define WOLFSSL_ESPWROOM32` in `/path/to/wolfssl/IDE/Espressif/ESP-IDF/user_settings.h`\
-   Uncomment out `#define WOLFSSL_ESPWROOM32SE` in `/path/to/wolfssl/IDE/Espressif/ESP-IDF/user_settings.h`
+1. Uncomment out `#define WOLFSSL_ESPWROOM32SE` in `/path/to/wolfssl/IDE/Espressif/ESP-IDF/user_settings.h`
     * **Note:** crypt test will fail if enabled `WOLFSSL_ESPWROOM32SE`
-3. wolfSSL under ESP-IDF. Please see [README.md](https://github.com/wolfSSL/wolfssl/blob/master/IDE/Espressif/ESP-IDF/README.md)
-4. CryptoAuthentication Library under ESP-IDF. Please see [README.md](https://github.com/miyazakh/cryptoauthlib_esp_idf/blob/master/README.md)
+2. wolfSSL under ESP-IDF. Please see [README.md](https://github.com/wolfSSL/wolfssl/blob/master/IDE/Espressif/ESP-IDF/README.md)
+3. CryptoAuthentication Library under ESP-IDF. Please see [README.md](https://github.com/miyazakh/cryptoauthlib_esp_idf/blob/master/README.md)
 
 ## Configuration
 1. The `user_settings.h` can be found in `/path/to/esp-idf/components/wolfssl/include/user_settings.h`

diff --git a/IDE/Espressif/ESP-IDF/examples/wolfssl_benchmark/components/wolfssl/CMakeLists.txt b/IDE/Espressif/ESP-IDF/examples/wolfssl_benchmark/components/wolfssl/CMakeLists.txt
@@ -190,6 +190,8 @@ set(COMPONENT_SRCEXCLUDE
     "${WOLFSSL_ROOT}/src/conf.c"
     "${WOLFSSL_ROOT}/src/misc.c"
     "${WOLFSSL_ROOT}/src/pk.c"
+    "${WOLFSSL_ROOT}/src/ssl_asn1.c" # included by ssl.c
+    "${WOLFSSL_ROOT}/src/ssl_bn.c" # included by ssl.c
     "${WOLFSSL_ROOT}/src/ssl_misc.c" # included by ssl.c
     "${WOLFSSL_ROOT}/src/x509.c"
     "${WOLFSSL_ROOT}/src/x509_str.c"

diff --git a/IDE/Espressif/ESP-IDF/examples/wolfssl_client/components/wolfssl/CMakeLists.txt b/IDE/Espressif/ESP-IDF/examples/wolfssl_client/components/wolfssl/CMakeLists.txt
@@ -190,6 +190,8 @@ set(COMPONENT_SRCEXCLUDE
     "${WOLFSSL_ROOT}/src/conf.c"
     "${WOLFSSL_ROOT}/src/misc.c"
     "${WOLFSSL_ROOT}/src/pk.c"
+    "${WOLFSSL_ROOT}/src/ssl_asn1.c" # included by ssl.c
+    "${WOLFSSL_ROOT}/src/ssl_bn.c" # included by ssl.c
     "${WOLFSSL_ROOT}/src/ssl_misc.c" # included by ssl.c
     "${WOLFSSL_ROOT}/src/x509.c"
     "${WOLFSSL_ROOT}/src/x509_str.c"

diff --git a/IDE/Espressif/ESP-IDF/examples/wolfssl_server/components/wolfssl/CMakeLists.txt b/IDE/Espressif/ESP-IDF/examples/wolfssl_server/components/wolfssl/CMakeLists.txt
@@ -190,6 +190,8 @@ set(COMPONENT_SRCEXCLUDE
     "${WOLFSSL_ROOT}/src/conf.c"
     "${WOLFSSL_ROOT}/src/misc.c"
     "${WOLFSSL_ROOT}/src/pk.c"
+    "${WOLFSSL_ROOT}/src/ssl_asn1.c" # included by ssl.c
+    "${WOLFSSL_ROOT}/src/ssl_bn.c" # included by ssl.c
     "${WOLFSSL_ROOT}/src/ssl_misc.c" # included by ssl.c
     "${WOLFSSL_ROOT}/src/x509.c"
     "${WOLFSSL_ROOT}/src/x509_str.c"

diff --git a/IDE/Espressif/ESP-IDF/examples/wolfssl_test/components/wolfssl/CMakeLists.txt b/IDE/Espressif/ESP-IDF/examples/wolfssl_test/components/wolfssl/CMakeLists.txt
@@ -190,6 +190,8 @@ set(COMPONENT_SRCEXCLUDE
     "${WOLFSSL_ROOT}/src/conf.c"
     "${WOLFSSL_ROOT}/src/misc.c"
     "${WOLFSSL_ROOT}/src/pk.c"
+    "${WOLFSSL_ROOT}/src/ssl_asn1.c" # included by ssl.c
+    "${WOLFSSL_ROOT}/src/ssl_bn.c" # included by ssl.c
     "${WOLFSSL_ROOT}/src/ssl_misc.c" # included by ssl.c
     "${WOLFSSL_ROOT}/src/x509.c"
     "${WOLFSSL_ROOT}/src/x509_str.c"

diff --git a/IDE/Espressif/ESP-IDF/examples/wolfssl_test/main/main.c b/IDE/Espressif/ESP-IDF/examples/wolfssl_test/main/main.c
@@ -152,37 +152,47 @@ void app_main(void)
 
 
     /* some interesting settings are target specific (ESP32, -C3, -S3, etc */
-#if defined(CONFIG_IDF_TARGET_ESP32C3)
-    /* not available for C3 at this time */
-#elif defined(CONFIG_IDF_TARGET_ESP32S3)
-    ESP_LOGI(TAG, "CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ = %u MHz",
-                   CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ
-             );
-    ESP_LOGI(TAG, "Xthal_have_ccount = %u", Xthal_have_ccount);
+#include <esp_idf_version.h>
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 0, 0)
+    #define CONFIG_IDF_TARGET_NAME ESP
 #else
-    ESP_LOGI(TAG, "CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ = %u MHz",
-                   CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ
+    #if defined(CONFIG_IDF_TARGET_ESP32)
+        #define CONFIG_IDF_TARGET_NAME ESP32
+    #elif defined(CONFIG_IDF_TARGET_ESP32S2)
+        #define CONFIG_IDF_TARGET_NAME ESP32S2
+    #elif defined(CONFIG_IDF_TARGET_ESP32S3)
+        #define CONFIG_IDF_TARGET_NAME ESP32S3
+    #elif defined(CONFIG_IDF_TARGET_ESP32H2)
+        #define CONFIG_IDF_TARGET_NAME ESP32H2
+    #elif defined(CONFIG_IDF_TARGET_ESP32C3)
+        #define CONFIG_IDF_TARGET_NAME ESP32C3
+    #else
+        #error CONFIG_IDF_TARGET " not supported"
+    #endif
+#endif
+
+#define LOG_TARGET_FREQ_INT(target) \
+    ESP_LOGI(TAG, "CONFIG_" #target "_DEFAULT_CPU_FREQ_MHZ = %u MHz", \
+                   CONFIG_##target##_DEFAULT_CPU_FREQ_MHZ \
             );
+#define LOG_TARGET_FREQ(target) LOG_TARGET_FREQ_INT(target)
+
+    LOG_TARGET_FREQ(CONFIG_IDF_TARGET_NAME);
+
+#if defined(CONFIG_IDF_TARGET_ARCH_XTENSA)
     ESP_LOGI(TAG, "Xthal_have_ccount = %u", Xthal_have_ccount);
 #endif
 
     /* all platforms: stack high water mark check */
     ESP_LOGI(TAG, "Stack HWM: %d\n", uxTaskGetStackHighWaterMark(NULL));
 
     /* check to see if we are using hardware encryption */
-#if defined(NO_ESP32WROOM32_CRYPT)
-    ESP_LOGI(TAG, "NO_ESP32WROOM32_CRYPT defined! HW acceleration DISABLED.");
-#else
-    #if defined(CONFIG_IDF_TARGET_ESP32C3)
-        #error "ESP32WROOM32_CRYPT not yet supported on ESP32-C3"
-    #elif defined(CONFIG_IDF_TARGET_ESP32S2)
-        #error "ESP32WROOM32_CRYPT not yet supported on ESP32-S2"
-    #elif defined(CONFIG_IDF_TARGET_ESP32S3)
-        #error "ESP32WROOM32_CRYPT not yet supported on ESP32-S3"
-    #else
-        ESP_LOGI(TAG, "ESP32WROOM32_CRYPT is enabled.");
-    #endif
-#endif
+    ESP_LOGI(TAG, "WOLFSSL_ESP_CRYPT_RSA_PRI is %s.", 
+             WOLFSSL_ESP_CRYPT_RSA_PRI ? "enabled" : "disabled");
+    ESP_LOGI(TAG, "WOLFSSL_ESP_CRYPT_HASH is %s.", 
+             WOLFSSL_ESP_CRYPT_HASH ? "enabled" : "disabled");
+    ESP_LOGI(TAG, "WOLFSSL_ESP_CRYPT_AES is %s.", 
+             WOLFSSL_ESP_CRYPT_AES ? "enabled" : "disabled");
 
 
 

diff --git a/IDE/Espressif/ESP-IDF/examples/wolfssl_test_idf/main/main.c b/IDE/Espressif/ESP-IDF/examples/wolfssl_test_idf/main/main.c
@@ -152,37 +152,47 @@ void app_main(void)
 
 
     /* some interesting settings are target specific (ESP32, -C3, -S3, etc */
-#if defined(CONFIG_IDF_TARGET_ESP32C3)
-    /* not available for C3 at this time */
-#elif defined(CONFIG_IDF_TARGET_ESP32S3)
-    ESP_LOGI(TAG, "CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ = %u MHz",
-                   CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ
-             );
-    ESP_LOGI(TAG, "Xthal_have_ccount = %u", Xthal_have_ccount);
+#include <esp_idf_version.h>
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 0, 0)
+    #define CONFIG_IDF_TARGET_NAME ESP
 #else
-    ESP_LOGI(TAG, "CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ = %u MHz",
-                   CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ
+    #if defined(CONFIG_IDF_TARGET_ESP32)
+        #define CONFIG_IDF_TARGET_NAME ESP32
+    #elif defined(CONFIG_IDF_TARGET_ESP32S2)
+        #define CONFIG_IDF_TARGET_NAME ESP32S2
+    #elif defined(CONFIG_IDF_TARGET_ESP32S3)
+        #define CONFIG_IDF_TARGET_NAME ESP32S3
+    #elif defined(CONFIG_IDF_TARGET_ESP32H2)
+        #define CONFIG_IDF_TARGET_NAME ESP32H2
+    #elif defined(CONFIG_IDF_TARGET_ESP32C3)
+        #define CONFIG_IDF_TARGET_NAME ESP32C3
+    #else
+        #error CONFIG_IDF_TARGET " not supported"
+    #endif
+#endif
+
+#define LOG_TARGET_FREQ_INT(target) \
+    ESP_LOGI(TAG, "CONFIG_" #target "_DEFAULT_CPU_FREQ_MHZ = %u MHz", \
+                   CONFIG_##target##_DEFAULT_CPU_FREQ_MHZ \
             );
+#define LOG_TARGET_FREQ(target) LOG_TARGET_FREQ_INT(target)
+
+    LOG_TARGET_FREQ(CONFIG_IDF_TARGET_NAME);
+
+#if defined(CONFIG_IDF_TARGET_ARCH_XTENSA)
     ESP_LOGI(TAG, "Xthal_have_ccount = %u", Xthal_have_ccount);
 #endif
 
     /* all platforms: stack high water mark check */
     ESP_LOGI(TAG, "Stack HWM: %d\n", uxTaskGetStackHighWaterMark(NULL));
 
     /* check to see if we are using hardware encryption */
-#if defined(NO_ESP32WROOM32_CRYPT)
-    ESP_LOGI(TAG, "NO_ESP32WROOM32_CRYPT defined! HW acceleration DISABLED.");
-#else
-    #if defined(CONFIG_IDF_TARGET_ESP32C3)
-        #error "ESP32WROOM32_CRYPT not yet supported on ESP32-C3"
-    #elif defined(CONFIG_IDF_TARGET_ESP32S2)
-        #error "ESP32WROOM32_CRYPT not yet supported on ESP32-S2"
-    #elif defined(CONFIG_IDF_TARGET_ESP32S3)
-        #error "ESP32WROOM32_CRYPT not yet supported on ESP32-S3"
-    #else
-        ESP_LOGI(TAG, "ESP32WROOM32_CRYPT is enabled.");
-    #endif
-#endif
+    ESP_LOGI(TAG, "WOLFSSL_ESP_CRYPT_RSA_PRI is %s.", 
+             WOLFSSL_ESP_CRYPT_RSA_PRI ? "enabled" : "disabled");
+    ESP_LOGI(TAG, "WOLFSSL_ESP_CRYPT_HASH is %s.", 
+             WOLFSSL_ESP_CRYPT_HASH ? "enabled" : "disabled");
+    ESP_LOGI(TAG, "WOLFSSL_ESP_CRYPT_AES is %s.", 
+             WOLFSSL_ESP_CRYPT_AES ? "enabled" : "disabled");
 
 
 

diff --git a/IDE/Espressif/ESP-IDF/examples/wolfssl_test_idf/main/main_wip.c.ex b/IDE/Espressif/ESP-IDF/examples/wolfssl_test_idf/main/main_wip.c.ex
@@ -196,37 +196,47 @@ void app_main(void)
 
 
     /* some interesting settings are target specific (ESP32, -C3, -S3, etc */
-#if defined(CONFIG_IDF_TARGET_ESP32C3)
-    /* not available for C3 at this time */
-#elif defined(CONFIG_IDF_TARGET_ESP32S3)
-    ESP_LOGI(TAG, "CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ = %u MHz",
-                   CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ
-             );
-    ESP_LOGI(TAG, "Xthal_have_ccount = %u", Xthal_have_ccount);
+#include <esp_idf_version.h>
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 0, 0)
+    #define CONFIG_IDF_TARGET_NAME ESP
 #else
-    ESP_LOGI(TAG, "CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ = %u MHz",
-                   CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ
+    #if defined(CONFIG_IDF_TARGET_ESP32)
+        #define CONFIG_IDF_TARGET_NAME ESP32
+    #elif defined(CONFIG_IDF_TARGET_ESP32S2)
+        #define CONFIG_IDF_TARGET_NAME ESP32S2
+    #elif defined(CONFIG_IDF_TARGET_ESP32S3)
+        #define CONFIG_IDF_TARGET_NAME ESP32S3
+    #elif defined(CONFIG_IDF_TARGET_ESP32H2)
+        #define CONFIG_IDF_TARGET_NAME ESP32H2
+    #elif defined(CONFIG_IDF_TARGET_ESP32C3)
+        #define CONFIG_IDF_TARGET_NAME ESP32C3
+    #else
+        #error CONFIG_IDF_TARGET " not supported"
+    #endif
+#endif
+
+#define LOG_TARGET_FREQ_INT(target) \
+    ESP_LOGI(TAG, "CONFIG_" #target "_DEFAULT_CPU_FREQ_MHZ = %u MHz", \
+                   CONFIG_##target##_DEFAULT_CPU_FREQ_MHZ \
             );
+#define LOG_TARGET_FREQ(target) LOG_TARGET_FREQ_INT(target)
+
+    LOG_TARGET_FREQ(CONFIG_IDF_TARGET_NAME);
+
+#if defined(CONFIG_IDF_TARGET_ARCH_XTENSA)
     ESP_LOGI(TAG, "Xthal_have_ccount = %u", Xthal_have_ccount);
 #endif
 
     /* all platforms: stack high water mark check */
     ESP_LOGI(TAG, "Stack HWM: %d\n", uxTaskGetStackHighWaterMark(NULL));
 
     /* check to see if we are using hardware encryption */
-#if defined(NO_ESP32WROOM32_CRYPT)
-    ESP_LOGI(TAG, "NO_ESP32WROOM32_CRYPT defined! HW acceleration DISABLED.");
-#else
-    #if defined(CONFIG_IDF_TARGET_ESP32C3)
-        #error "ESP32WROOM32_CRYPT not yet supported on ESP32-C3"
-    #elif defined(CONFIG_IDF_TARGET_ESP32S2)
-        #error "ESP32WROOM32_CRYPT not yet supported on ESP32-S2"
-    #elif defined(CONFIG_IDF_TARGET_ESP32S3)
-        #error "ESP32WROOM32_CRYPT not yet supported on ESP32-S3"
-    #else
-        ESP_LOGI(TAG, "ESP32WROOM32_CRYPT is enabled.");
-    #endif
-#endif
+    ESP_LOGI(TAG, "WOLFSSL_ESP_CRYPT_RSA_PRI is %s.", 
+             WOLFSSL_ESP_CRYPT_RSA_PRI ? "enabled" : "disabled");
+    ESP_LOGI(TAG, "WOLFSSL_ESP_CRYPT_HASH is %s.", 
+             WOLFSSL_ESP_CRYPT_HASH ? "enabled" : "disabled");
+    ESP_LOGI(TAG, "WOLFSSL_ESP_CRYPT_AES is %s.", 
+             WOLFSSL_ESP_CRYPT_AES ? "enabled" : "disabled");
 
 
 

diff --git a/IDE/Espressif/ESP-IDF/libs/CMakeLists.txt b/IDE/Espressif/ESP-IDF/libs/CMakeLists.txt
@@ -71,6 +71,8 @@ set(COMPONENT_SRCEXCLUDE
     "./src/conf.c"
     "./src/misc.c"
     "./src/pk.c"
+    "./src/ssl_asn1.c" # included by ssl.c
+    "./src/ssl_bn.c" # included by ssl.c
     "./src/ssl_misc.c" # included by ssl.c
     "./src/x509.c"
     "./src/x509_str.c"

diff --git a/IDE/Espressif/ESP-IDF/test/component.mk b/IDE/Espressif/ESP-IDF/test/component.mk
@@ -5,6 +5,6 @@
 #CFLAGS := -v
 CFLAGS += -DNO_MAIN_DRIVER
 CFLAGS += -DWOLFSSL_USER_SETTINGS
-#CFLAGS += -DWOLFSSL_ESP32WROOM32_CRYPT_DEBUG
+#CFLAGS += -DWOLFSSL_ESP32_CRYPT_DEBUG
 
 COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive
diff --git a/IDE/Espressif/ESP-IDF/user_settings.h b/IDE/Espressif/ESP-IDF/user_settings.h
@@ -19,22 +19,22 @@
  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
  */
 #undef WOLFSSL_ESPIDF
-#undef WOLFSSL_ESPWROOM32
 #undef WOLFSSL_ESPWROOM32SE
-#undef WOLFSSL_ESPWROOM32
-#undef WOLFSSL_ESP8266
 
 #define WOLFSSL_ESPIDF
 
 /*
- * choose ONE of these Espressif chips to define:
+ * Define WOLFSSL_ESPWROOM32SE to enable additional support for the external
+ * ATECC608A on the ESP32-WROOM32SE
  *
- * WOLFSSL_ESPWROOM32
- * WOLFSSL_ESPWROOM32SE
- * WOLFSSL_ESP8266
+ * #define WOLFSSL_ESPWROOM32SE
  */
 
-#define WOLFSSL_ESPWROOM32
+/* when you want not to use HW acceleration */
+/* #define NO_ESP32_CRYPT */
+/* #define NO_WOLFSSL_ESP32_CRYPT_HASH*/
+/* #define NO_WOLFSSL_ESP32_CRYPT_AES */
+/* #define NO_WOLFSSL_ESP32_CRYPT_RSA_PRI */
 
 /* #define DEBUG_WOLFSSL_VERBOSE */
 
@@ -86,7 +86,8 @@
 #endif
 
 /* rsa primitive specific definition */
-#if defined(WOLFSSL_ESPWROOM32) || defined(WOLFSSL_ESPWROOM32SE)
+#if defined(CONFIG_IDF_TARGET_ESP32) && \
+    !defined(NO_WOLFSSL_ESP32_CRYPT_RSA_PRI)
     /* Define USE_FAST_MATH and SMALL_STACK                        */
     #define ESP32_USE_RSA_PRIMITIVE
     /* threshold for performance adjustment for hw primitive use   */
@@ -98,7 +99,7 @@
 
 /* debug options */
 /* #define DEBUG_WOLFSSL */
-/* #define WOLFSSL_ESP32WROOM32_CRYPT_DEBUG */
+/* #define WOLFSSL_ESP32_CRYPT_DEBUG */
 /* #define WOLFSSL_ATECC508A_DEBUG          */
 
 /* date/time                               */
@@ -107,11 +108,5 @@
 /* #define NO_ASN_TIME */
 /* #define XTIME time */
 
-/* when you want not to use HW acceleration */
-/* #define NO_ESP32WROOM32_CRYPT */
-/* #define NO_WOLFSSL_ESP32WROOM32_CRYPT_HASH*/
-/* #define NO_WOLFSSL_ESP32WROOM32_CRYPT_AES */
-/* #define NO_WOLFSSL_ESP32WROOM32_CRYPT_RSA_PRI */
-
 /* adjust wait-timeout count if you see timeout in rsa hw acceleration */
 #define ESP_RSA_TIMEOUT_CNT    0x249F00