Skip to content

[Bugfix] Fix single output condition in output processor #7881

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Merged
merged 1 commit into from
Sep 3, 2024
Merged

[Bugfix] Fix single output condition in output processor #7881

merged 1 commit into from
Sep 3, 2024

Conversation

WoosukKwon
Copy link
Collaborator

@github-actions GitHub Actions
Copy link

👋 Hi! Thank you for contributing to the vLLM project.
Just a reminder: PRs would not trigger full CI run by default. Instead, it would only run fastcheck CI which consists a small and essential subset of CI tests to quickly catch errors. You can run other CI tests on top of default ones by unblocking the steps in your fast-check build on Buildkite UI.

Once the PR is approved and ready to go, please make sure to run full CI as it is required to merge (or just use auto-merge).

To run full CI, you can do one of these:

  • Comment /ready on the PR
  • Add ready label to the PR
  • Enable auto-merge.

🚀

@WoosukKwon WoosukKwon mentioned this pull request Aug 26, 2024
Merged
6 tasks
alexm-redhat added a commit to megha95/vllm that referenced this pull request Aug 26, 2024
@alexm-redhat
Sync with Woosuk change in vllm-project#7881
65dd781
@WoosukKwon WoosukKwon merged commit 0fbc669 into main Sep 3, 2024
29 checks passed
@WoosukKwon WoosukKwon deleted the fix-single-step branch September 3, 2024 03:35
@DarkLight1337
Copy link
Member

DarkLight1337 commented Sep 3, 2024 •
edited
Loading

LoRA test is still partially failing. https://buildkite.com/vllm/fastcheck/builds/3171#01919067-9dfa-4303-8d50-3ea094dac854

Alvant pushed a commit to compressa-ai/vllm that referenced this pull request Oct 26, 2024
@WoosukKwon @Alvant
[Bugfix] Fix single output condition in output processor (vllm-projec…
9e466a7 
…t#7881)

Signed-off-by: Alvant <[email protected]>
LeiWang1999 pushed a commit to LeiWang1999/vllm-bitblas that referenced this pull request Mar 26, 2025
@WoosukKwon @LeiWang1999
[Bugfix] Fix single output condition in output processor (vllm-projec…
80d7c45 
…t#7881)

Signed-off-by: LeiWang1999 <[email protected]>
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers
No reviews
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
2 participants
@WoosukKwon @DarkLight1337