SystemVerilog: implement unsupported features in processDesignElement()

[hirooih]

• processDesignElement() is divided into processDesignElementL() (for module, interface, and program) and processDesignElementS() (for others).
• tagging imported functions is implemented
• skipping package import declaration is implemented
• implement "interface class" support
• implement coverage_event handling
• units tests are heavily updated

[coveralls]

Coverage increased (+0.0008%) to 86.982% when pulling 977cdf2 on hirooih:sv-design-element into de31d3e on universal-ctags:master.

[codecov]

Codecov Report

Merging #2737 (977cdf2) into master (7f84a44) will increase coverage by 0.05%.
The diff coverage is 95.74%.

@@            Coverage Diff             @@
##           master    #2737      +/-   ##
==========================================
+ Coverage   86.83%   86.89%   +0.05%     
==========================================
  Files         189      190       +1     
  Lines       40256    40351      +95     
==========================================
+ Hits        34958    35063     +105     
+ Misses       5298     5288      -10     

Impacted Files	Coverage Δ
parsers/verilog.c	97.94% <95.74%> (-0.25%)	⬇️
parsers/txt2tags.c	100.00% <0.00%> (ø)
parsers/php.c	94.46% <0.00%> (+1.83%)	⬆️

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[masatake]

(just comment) I recommend adding "," at the end. So we can make diff smaller when you add a new keyword next time.

[hirooih]

I know modern languages allow this, but I have been misunderstanding that C did not allowed this.

I've checked the K&R both the 1st and the 2nd edition, Most of examples do not use semicolon after the last item, but syntax rule says;

initializer:
	assignment-expression
	{ initializer-list }
	{ initializer-list , }


initializer-list:
	initializer
	initializer-list , initializer

Verilog/SystemVerilog does not allow this, it makes difficult scripting...

Thank!!!

[masatake]

How should we handle "import", "using", "load", "require", "include", etc is one of the hard topic in ctags.
Of course, skipping it is the first step. If you have time, please, watch #2697 and #2727.

[hirooih]

How should we handle "import", "using", "load", "require", "include", etc is one of the hard topic in ctags.

For import of System Verilog, it is not hard topic. Adding a field should be enough. I will add it on the TODO this.