Add bus lock feature #1245
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Add bus lock feature #1245
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addition to #1236
is "error" a reserved keyword?
stnolting
added
enhancement
-> experimental
add lock signal
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This PR adds a new status signal (
lock) to the processor-internal request bus. When set, the bus infrastructure gives priority to this bus transaction and does not allow any interruptions. This reduces waite states when transferring larger memory blocks (e.g. cache blocks).Without Bus Lock
Cache block updates (cache line = 8x32-bit) issues by both CPU cores are interleaved.
With Bus Lock
Cache block updates (cache line = 8x32-bit) complete one after another.
Next step: cache bursts.