Risc-V CPU design and some verilog designs for different tasks

1A. Frequency Scaling & PWM Generation

1B. Color Detection using Frequency Detection

1C. RISC-V CPU Design

2A. UART

2B. Path Planner on RISC-V CPU

All of the simulations are done using modelsim and Intel Quartus prime lite

Whole code is written in verilog except for the path planning algorithm (Djikstras)

• Amey Jawale
• Atharva Wadnere
• Shrikar Dongre
• Karan lalwani