Feat: accurate cycle tracker

crates/circuits/mod-builder/src/core_chip.rs

@@ -425,6 +425,7 @@ where
             &mut adapter_record,
         );
 
+        *state.instret += 1;
         *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
         Ok(())
     }

crates/vm/src/arch/execution.rs

@@ -216,6 +216,7 @@ pub trait PreflightExecutor<F, RA = MatrixRecordArena<F>> {
 #[derive(derive_new::new)]
 pub struct VmStateMut<'a, F, MEM, RA> {
     pub pc: &'a mut u32,
+    pub instret: &'a mut u64,
     pub memory: &'a mut MEM,
     pub streams: &'a mut Streams<F>,
     pub rng: &'a mut StdRng,

crates/vm/src/arch/state.rs

@@ -67,6 +67,7 @@ impl<F: Clone, MEM> VmState<F, MEM> {
     pub fn into_mut<'a, RA>(&'a mut self, ctx: &'a mut RA) -> VmStateMut<'a, F, MEM, RA> {
         VmStateMut {
             pc: &mut self.pc,
+            instret: &mut self.instret,
             memory: &mut self.memory,
             streams: &mut self.streams,
             rng: &mut self.rng,

crates/vm/src/arch/testing/cpu.rs

@@ -98,8 +98,10 @@ where
         tracing::debug!("initial_timestamp={}", self.memory.memory.timestamp());
 
         let mut pc = initial_pc;
+        let mut instret = 0;
         let state_mut = VmStateMut {
             pc: &mut pc,
+            instret: &mut instret,
             memory: &mut self.memory.memory,
             streams: &mut self.streams,
             rng: &mut self.rng,

crates/vm/src/arch/testing/cuda.rs

@@ -132,8 +132,10 @@ impl TestBuilder<F> for GpuChipTestBuilder {
         tracing::debug!("initial_timestamp={}", initial_state.timestamp);
 
         let mut pc = initial_pc;
+        let mut instret = 0;
         let state_mut = VmStateMut::new(
             &mut pc,
+            &mut instret,
             &mut self.memory.memory,
             &mut self.streams,
             &mut self.rng,

crates/vm/src/system/phantom/mod.rs

@@ -157,14 +157,18 @@ where
                 SysPhantom::CtStart => {
                     let metrics = state.metrics;
                     if let Some(info) = metrics.debug_infos.get(pc) {
-                        metrics.cycle_tracker.start(info.dsl_instruction.clone());
+                        metrics
+                            .cycle_tracker
+                            .start(info.dsl_instruction.clone(), *state.instret as usize);
                     }
                 }
                 #[cfg(feature = "perf-metrics")]
                 SysPhantom::CtEnd => {
                     let metrics = state.metrics;
                     if let Some(info) = metrics.debug_infos.get(pc) {
-                        metrics.cycle_tracker.end(info.dsl_instruction.clone());
+                        metrics
+                            .cycle_tracker
+                            .end(info.dsl_instruction.clone(), *state.instret as usize);
                     }
                 }
                 _ => {}
@@ -187,6 +191,7 @@ where
                     inner: err,
                 })?;
         }
+        *state.instret += 1;
         *state.pc += DEFAULT_PC_STEP;
         state.memory.increment_timestamp();
 

crates/vm/src/system/public_values/core.rs

@@ -202,6 +202,7 @@ where
             }
         }
 
+        *state.instret += 1;
         *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
 
         Ok(())

extensions/keccak256/circuit/src/trace.rs

@@ -235,6 +235,7 @@ where
         }
 
         // Due to the AIR constraints, the final memory timestamp should be the following:
+        *state.instret += 1;
         state.memory.timestamp = record.inner.timestamp
             + (len + KECCAK_REGISTER_READS + KECCAK_ABSORB_READS + KECCAK_DIGEST_WRITES) as u32;
         *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);

extensions/native/circuit/src/branch_eq/core.rs

@@ -76,6 +76,8 @@ where
             *state.pc = state.pc.wrapping_add(self.pc_step);
         }
 
+        *state.instret += 1;
+
         Ok(())
     }
 }

extensions/native/circuit/src/castf/core.rs

@@ -157,6 +157,7 @@ where
         self.adapter
             .write(state.memory, instruction, x, &mut adapter_record);
 
+        *state.instret += 1;
         *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
 
         Ok(())

extensions/native/circuit/src/field_arithmetic/core.rs

@@ -163,6 +163,7 @@ where
         self.adapter
             .write(state.memory, instruction, [a_val], &mut adapter_record);
 
+        *state.instret += 1;
         *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
 
         Ok(())

extensions/native/circuit/src/field_extension/core.rs

@@ -194,6 +194,7 @@ where
         self.adapter
             .write(state.memory, instruction, x, &mut adapter_record);
 
+        *state.instret += 1;
         *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
 
         Ok(())

extensions/native/circuit/src/fri/mod.rs

@@ -887,6 +887,7 @@ where
         );
         record.common.result_ptr = e;
 
+        *state.instret += 1;
         *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
 
         Ok(())

extensions/native/circuit/src/jal_rangecheck/mod.rs

@@ -233,6 +233,8 @@ where
             *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
         }
 
+        *state.instret += 1;
+
         Ok(())
     }
 }

extensions/native/circuit/src/loadstore/core.rs

@@ -175,6 +175,7 @@ where
         core_record.pointer_read = pointer_read;
         core_record.data = data;
 
+        *state.instret += 1;
         *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
 
         Ok(())

extensions/native/circuit/src/poseidon2/chip.rs

@@ -827,6 +827,7 @@ where
             unreachable!()
         }
 
+        *state.instret += 1;
         *state.pc += DEFAULT_PC_STEP;
         Ok(())
     }

extensions/native/circuit/src/sumcheck/chip.rs

@@ -481,6 +481,7 @@ where
         }
         assert_eq!(eval_acc, elem_to_ext(F::from_canonical_u32(0)),);
 
+        *state.instret += 1;
         *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
         Ok(())
     }

extensions/rv32im/circuit/src/auipc/core.rs

@@ -238,6 +238,7 @@ where
         self.adapter
             .write(state.memory, instruction, rd, &mut adapter_record);
 
+        *state.instret += 1;
         *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
 
         Ok(())

extensions/rv32im/circuit/src/base_alu/core.rs

@@ -231,6 +231,7 @@ where
         self.adapter
             .write(state.memory, instruction, [rd].into(), &mut adapter_record);
 
+        *state.instret += 1;
         *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
 
         Ok(())

extensions/rv32im/circuit/src/branch_eq/core.rs

@@ -199,6 +199,8 @@ where
             *state.pc = state.pc.wrapping_add(self.pc_step);
         }
 
+        *state.instret += 1;
+
         Ok(())
     }
 }

extensions/rv32im/circuit/src/branch_lt/core.rs

@@ -253,6 +253,8 @@ where
             *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
         }
 
+        *state.instret += 1;
+
         Ok(())
     }
 }

extensions/rv32im/circuit/src/divrem/core.rs

@@ -456,6 +456,7 @@ where
         self.adapter
             .write(state.memory, instruction, [rd].into(), &mut adapter_record);
 
+        *state.instret += 1;
         *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
 
         Ok(())

extensions/rv32im/circuit/src/hintstore/mod.rs

@@ -468,6 +468,7 @@ where
                 &mut record.var[idx].data_write_aux.prev_data,
             );
         }
+        *state.instret += 1;
         *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
 
         Ok(())

extensions/rv32im/circuit/src/jal_lui/core.rs

@@ -203,6 +203,7 @@ where
             .write(state.memory, instruction, rd_data, &mut adapter_record);
 
         *state.pc = to_pc;
+        *state.instret += 1;
 
         Ok(())
     }

extensions/rv32im/circuit/src/jalr/core.rs

@@ -267,6 +267,8 @@ where
         // RISC-V spec explicitly sets the least significant bit of `to_pc` to 0
         *state.pc = to_pc & !1;
 
+        *state.instret += 1;
+
         Ok(())
     }
 }

extensions/rv32im/circuit/src/less_than/core.rs

@@ -242,6 +242,7 @@ where
             &mut adapter_record,
         );
 
+        *state.instret += 1;
         *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
 
         Ok(())

extensions/rv32im/circuit/src/load_sign_extend/core.rs

@@ -257,6 +257,7 @@ where
             &mut adapter_record,
         );
 
+        *state.instret += 1;
         *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
 
         Ok(())

extensions/rv32im/circuit/src/loadstore/core.rs

@@ -314,6 +314,7 @@ where
         self.adapter
             .write(state.memory, instruction, write_data, &mut adapter_record);
 
+        *state.instret += 1;
         *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
 
         Ok(())

extensions/rv32im/circuit/src/mul/core.rs

@@ -211,6 +211,7 @@ where
         self.adapter
             .write(state.memory, instruction, [a].into(), &mut adapter_record);
 
+        *state.instret += 1;
         *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
         Ok(())
     }

extensions/rv32im/circuit/src/mulh/core.rs

@@ -286,6 +286,7 @@ where
         self.adapter
             .write(state.memory, instruction, [a].into(), &mut adapter_record);
 
+        *state.instret += 1;
         *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
 
         Ok(())

extensions/rv32im/circuit/src/shift/core.rs

@@ -338,6 +338,7 @@ where
             [output].into(),
             &mut adapter_record,
         );
+        *state.instret += 1;
         *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
 
         Ok(())

extensions/sha256/circuit/src/sha256_chip/trace.rs

@@ -239,6 +239,7 @@ where
             &mut record.inner.write_aux.prev_data,
         );
 
+        *state.instret += 1;
         *state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
 
         Ok(())