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2 parents d40bea9 + 549d2a7 commit d4b91cbCopy full SHA for d4b91cb
src/registers/esr_el1.rs
@@ -54,10 +54,6 @@ register_bitfields! {u64,
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TrappedMSRR_MRRS = 0b01_0100,
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/// SVC instruction execution in AArch64 state
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SVC64 = 0b01_0101,
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- /// HVC instruction execution in AArch64 state
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- HVC64 = 0b01_0110,
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- /// SMC instruction execution in AArch64 state
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- SMC64 = 0b01_0111,
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/// Trapped MSR, MRS or System instruction execution in AArch64 state
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TrappedMsrMrs = 0b01_1000,
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/// Access to SVE functionality trapped (FEAT_SVE)
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