This is my version of a RISCV Microcontroller. Currently, it is a Vivado 2022.2 project utilizing only SystemVerilog, and targetting the Basys 3 Artix-7 development board. It, at the moment, implements RV32I

The processor is based off of the OTTER MCU as designed in a Winter 2023 CPE 233 class The OTTER MCU design was made by Dr. Callenes-Sloan, Dr. Mealy, and Dr. Hummel at Cal Poly SLO.