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@SamuelRiedel SamuelRiedel commented Aug 20, 2024

Replace our manually managed control registers with automatically generated ones using reggen. This will make it easier to modify and add new control registers.

Changelog

Changed

  • Use automatically generated control registers

Checklist

  • Automated tests pass
  • Changelog updated
  • Code style guideline is observed

@SamuelRiedel SamuelRiedel force-pushed the sriedel/control-registers branch 2 times, most recently from 8782c50 to 9b2fa6b Compare August 20, 2024 15:53
@SamuelRiedel SamuelRiedel marked this pull request as ready for review August 20, 2024 16:02
This was referenced Aug 28, 2024
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Is the tool invoked every time we compile the RTL for simulation? If not, does it make sense to add a helper target in the hardware/Makefile similar to the one we use to generate the bootroom?

@SamuelRiedel SamuelRiedel force-pushed the sriedel/control-registers branch from 9b2fa6b to 2b27038 Compare September 17, 2024 12:03
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Is the tool invoked every time we compile the RTL for simulation? If not, does it make sense to add a helper target in the hardware/Makefile similar to the one we use to generate the bootroom?

I added a target that checks whether the HJSON was modified and that automatically updates the control register files in that case. It can also be used as the convenience target in the hardware/Makefile directly.

@SamuelRiedel SamuelRiedel merged commit 546baa4 into main Sep 17, 2024
@SamuelRiedel SamuelRiedel deleted the sriedel/control-registers branch September 17, 2024 12:46
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3 participants