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    317 repositories

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •90•199•9•7•Updated Jan 23, 2026Jan 23, 2026

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •37•135•5•13•Updated Jan 23, 2026Jan 23, 2026

    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      •
      Apache License 2.0
      •56•343•25•6•Updated Jan 23, 2026Jan 23, 2026

    • MAGIA

      Public
      Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.
      C
      •
      Apache License 2.0
      •5•18•1•1•Updated Jan 23, 2026Jan 23, 2026

    • AraXL

      Public
      C
      •
      Other
      •1•3•0•1•Updated Jan 23, 2026Jan 23, 2026

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •53•264•23•5•Updated Jan 22, 2026Jan 22, 2026

    • apb

      Public
      APB Logic
      SystemVerilog
      •
      Other
      •19•22•2•3•Updated Jan 22, 2026Jan 22, 2026

    • astral

      Public
      A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.
      cfpgaspaceacceleratorriscvsystemverilogmulticoresafety-criticalheterogeneous-computing
      SystemVerilog
      •
      Other
      •28•11•1•2•Updated Jan 22, 2026Jan 22, 2026

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicfpgasimulationriscvsystemverilogrtl-design
      Verilog
      •
      Other
      •94•315•17•23•Updated Jan 21, 2026Jan 21, 2026

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •878•21•1•7•Updated Jan 21, 2026Jan 21, 2026

    • ManyRVData

      Public
      C
      •2•2•0•1•Updated Jan 21, 2026Jan 21, 2026

    • axi_rt

      Public
      SystemVerilog
      •
      Other
      •5•4•9•0•Updated Jan 21, 2026Jan 21, 2026

    • datamover

      Public
      SystemVerilog
      •
      Other
      •1•1•1•1•Updated Jan 19, 2026Jan 19, 2026

    • hwpe-stream

      Public
      IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
      SystemVerilog
      •
      Other
      •24•21•3•5•Updated Jan 17, 2026Jan 17, 2026

    • hci

      Public
      Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
      SystemVerilog
      •
      Other
      •19•14•5•5•Updated Jan 17, 2026Jan 17, 2026

    • Insitu-Cache

      Public
      SystemVerilog
      •
      Other
      •2•3•0•0•Updated Jan 16, 2026Jan 16, 2026

    • clint

      Public
      RISC-V Core Local Interrupt Controller (CLINT)
      SystemVerilog
      •
      Other
      •7•29•0•1•Updated Jan 16, 2026Jan 16, 2026

    • chimera-sdk

      Public
      C
      •
      Apache License 2.0
      •9•4•5•5•Updated Jan 16, 2026Jan 16, 2026

    • control-pulp

      Public
      C
      •
      Other
      •3•5•1•2•Updated Jan 16, 2026Jan 16, 2026

    • cva6-sdk

      Public
      CVA6 SDK containing RISC-V tools and Buildroot
      Makefile
      •88•3•0•3•Updated Jan 16, 2026Jan 16, 2026

    • PeakRDL-rawheader

      Public
      Python
      •
      Apache License 2.0
      •1•0•0•0•Updated Jan 15, 2026Jan 15, 2026

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •94•121•16•1•Updated Jan 15, 2026Jan 15, 2026

    • pulp-nnx

      Public
      C
      •
      Apache License 2.0
      •4•8•0•1•Updated Jan 15, 2026Jan 15, 2026

    • magia-sdk

      Public
      C
      •6•4•0•1•Updated Jan 14, 2026Jan 14, 2026

    • DeepQuant

      Public
      A Python library for true quantization of neural networks
      Python
      •
      Apache License 2.0
      •4•8•1•4•Updated Jan 13, 2026Jan 13, 2026

    • picobello

      Public
      whatever it means
      C
      •
      Other
      •9•15•7•2•Updated Jan 12, 2026Jan 12, 2026

    • mempool

      Public
      A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •57•312•3•4•Updated Jan 12, 2026Jan 12, 2026

    • neureka

      Public
      2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
      SystemVerilog
      •
      Other
      •7•28•5•8•Updated Jan 12, 2026Jan 12, 2026

    • obi

      Public
      OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
      SystemVerilog
      •
      Other
      •12•19•2•7•Updated Jan 9, 2026Jan 9, 2026

    • scm

      Public
      SystemVerilog
      •
      Other
      •7•5•0•1•Updated Jan 8, 2026Jan 8, 2026