Optimized CSR stalls #917
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Optimized CSR stalls #917
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1: ID stage stalls are kept as before for implicit CSR reads (mret and tablejumps). They stall on any CSR accesses in EX or WB. 2: EX stage is stalled for: 2.1: CSR instruction reading multiple CSRs (imiiplicit reads) are stalled when any CSR access is in WB 2.2: CSR instructions are stalled when any implicit CSR write is in WB 2.3: CSR instructions are stalled on a true RAW hazard with another regular CSR instruction in WB. Signed-off-by: Oystein Knauserud <[email protected]>
Signed-off-by: Oystein Knauserud <[email protected]>
silabs-oysteink
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Component:RTL
Silabs-ArjanB
requested changes
Aug 25, 2023
…out stall signals being conservative i.e not factoring inn kill or halt. Signed-off-by: Oystein Knauserud <[email protected]>
Signed-off-by: Oystein Knauserud <[email protected]>
Silabs-ArjanB
requested changes
Aug 25, 2023
rtl/cv32e40x_controller_bypass.sv
Outdated
| ex_wb_pipe_i.csr_en && ex_wb_pipe_i.csr_impl_wr)); | ||
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| // Detect implicit and explicit CSR writes in EX | ||
| assign csr_write_in_ex = (id_ex_pipe_i.instr_valid && (id_ex_pipe_i.csr_en || csr_impl_write_in_ex)); |
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Remove unneeded outer brackets
Signed-off-by: Oystein Knauserud <[email protected]>
Silabs-ArjanB
approved these changes
Aug 28, 2023
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Conservatively stalling ID for any implicit CSR read while any implicit or explicit CSR write is in EX or WB (unchanged)
Conservatively stalling EX for any implicit CSR read while any implicit or explicit CSR write is in WB
Conservatively stalling EX for any explicit CSR rad while any implicit CSR write is in WB
Precisely stalling EX for any explicit CSR read while an explicit CSR write to the same CSR is in WB.