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Implemented DM_REGION #768

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Merged
merged 3 commits into from
Jan 25, 2023
Merged

Implemented DM_REGION #768

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22afba6
Added parameters DM_REGION_START and DM_REGION_END.
silabs-oysteink Jan 24, 2023
c2167e3
Signal rename and indentation fix.
silabs-oysteink Jan 24, 2023
fb37642
Updates after review.
silabs-oysteink Jan 25, 2023
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34 changes: 25 additions & 9 deletions bhv/cv32e40x_wrapper.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -70,7 +70,9 @@ module cv32e40x_wrapper
parameter int DBG_NUM_TRIGGERS = 1,
parameter int PMA_NUM_REGIONS = 0,
parameter pma_cfg_t PMA_CFG[PMA_NUM_REGIONS-1:0] = '{default:PMA_R_DEFAULT},
parameter bit CORE_LOG_ENABLE = 1
parameter bit CORE_LOG_ENABLE = 1,
parameter logic [31:0] DM_REGION_START = 32'hF0000000,
parameter logic [31:0] DM_REGION_END = 32'hF0003FFF
)
(
// Clock and Reset
Expand Down Expand Up @@ -381,13 +383,19 @@ endgenerate
cv32e40x_mpu_sva
#(.PMA_NUM_REGIONS (PMA_NUM_REGIONS),
.PMA_CFG (PMA_CFG),
.IS_INSTR_SIDE (1))
.IS_INSTR_SIDE (1),
.CORE_RESP_TYPE (cv32e40x_pkg::inst_resp_t),
.CORE_REQ_TYPE (cv32e40x_pkg::obi_inst_req_t),
.DM_REGION_START (DM_REGION_START),
.DM_REGION_END (DM_REGION_END))
mpu_if_sva(.pma_addr (pma_i.trans_addr_i),
.pma_cfg (pma_i.pma_cfg),
.pma_dbg (core_i.if_stage_i.mpu_i.core_trans_i.dbg),
.obi_memtype (core_i.instr_memtype_o),
.obi_addr (core_i.instr_addr_o),
.obi_req (core_i.instr_req_o),
.obi_gnt (core_i.instr_gnt_i),
.obi_dbg (core_i.instr_dbg_o),
.write_buffer_state (cv32e40x_pkg::WBUF_EMPTY),
.write_buffer_valid_o ('0),
.write_buffer_txn_bufferable ('0),
Expand All @@ -397,17 +405,23 @@ endgenerate
bind cv32e40x_mpu:
core_i.load_store_unit_i.mpu_i
cv32e40x_mpu_sva
#(.PMA_NUM_REGIONS(PMA_NUM_REGIONS),
.PMA_CFG(PMA_CFG),
.IS_INSTR_SIDE(0),
.CORE_RESP_TYPE(cv32e40x_pkg::data_resp_t),
.X_EXT (X_EXT))
mpu_lsu_sva(.pma_addr(pma_i.trans_addr_i),
.pma_cfg (pma_i.pma_cfg),
#(.PMA_NUM_REGIONS (PMA_NUM_REGIONS),
.PMA_CFG (PMA_CFG),
.IS_INSTR_SIDE (0),
.CORE_RESP_TYPE (cv32e40x_pkg::data_resp_t),
.CORE_REQ_TYPE (cv32e40x_pkg::obi_data_req_t),
.X_EXT (X_EXT),
.A_EXT (A_EXT),
.DM_REGION_START (DM_REGION_START),
.DM_REGION_END (DM_REGION_END))
mpu_lsu_sva(.pma_addr (pma_i.trans_addr_i),
.pma_cfg (pma_i.pma_cfg),
.pma_dbg (core_i.load_store_unit_i.mpu_i.core_trans_i.dbg),
.obi_memtype (core_i.data_memtype_o),
.obi_addr (core_i.data_addr_o),
.obi_req (core_i.data_req_o),
.obi_gnt (core_i.data_gnt_i),
.obi_dbg (core_i.data_dbg_o),
.write_buffer_state (core_i.load_store_unit_i.write_buffer_i.state),
.write_buffer_valid_o (core_i.load_store_unit_i.write_buffer_i.valid_o),
.write_buffer_txn_bufferable (core_i.load_store_unit_i.write_buffer_i.trans_o.memtype[0]),
Expand Down Expand Up @@ -750,6 +764,8 @@ endgenerate
.SMCLIC ( SMCLIC ),
.SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ),
.SMCLIC_INTTHRESHBITS ( SMCLIC_INTTHRESHBITS ),
.DM_REGION_START ( DM_REGION_START ),
.DM_REGION_END ( DM_REGION_END ),
.DBG_NUM_TRIGGERS ( DBG_NUM_TRIGGERS ),
.PMA_NUM_REGIONS ( PMA_NUM_REGIONS ),
.PMA_CFG ( PMA_CFG ))
Expand Down
10 changes: 8 additions & 2 deletions rtl/cv32e40x_core.sv
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Expand Up @@ -36,6 +36,8 @@ module cv32e40x_core import cv32e40x_pkg::*;
parameter bit A_EXT = 0,
parameter b_ext_e B_EXT = B_NONE,
parameter m_ext_e M_EXT = M,
parameter logic [31:0] DM_REGION_START = 32'hF0000000,
parameter logic [31:0] DM_REGION_END = 32'hF0003FFF,
parameter int DBG_NUM_TRIGGERS = 1,
parameter int PMA_NUM_REGIONS = 0,
parameter pma_cfg_t PMA_CFG[PMA_NUM_REGIONS-1:0] = '{default:PMA_R_DEFAULT},
Expand Down Expand Up @@ -436,7 +438,9 @@ module cv32e40x_core import cv32e40x_pkg::*;
.SMCLIC ( SMCLIC ),
.SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ),
.ZC_EXT ( ZC_EXT ),
.M_EXT ( M_EXT )
.M_EXT ( M_EXT ),
.DM_REGION_START ( DM_REGION_START ),
.DM_REGION_END ( DM_REGION_END )
)
if_stage_i
(
Expand Down Expand Up @@ -629,7 +633,9 @@ module cv32e40x_core import cv32e40x_pkg::*;
.X_ID_WIDTH (X_ID_WIDTH ),
.PMA_NUM_REGIONS (PMA_NUM_REGIONS ),
.PMA_CFG (PMA_CFG ),
.DBG_NUM_TRIGGERS (DBG_NUM_TRIGGERS )
.DBG_NUM_TRIGGERS (DBG_NUM_TRIGGERS ),
.DM_REGION_START (DM_REGION_START ),
.DM_REGION_END (DM_REGION_END )
)
load_store_unit_i
(
Expand Down
8 changes: 6 additions & 2 deletions rtl/cv32e40x_if_stage.sv
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Expand Up @@ -39,7 +39,9 @@ module cv32e40x_if_stage import cv32e40x_pkg::*;
parameter bit SMCLIC = 1'b0,
parameter int SMCLIC_ID_WIDTH = 5,
parameter bit ZC_EXT = 0,
parameter m_ext_e M_EXT = M_NONE
parameter m_ext_e M_EXT = M_NONE,
parameter logic [31:0] DM_REGION_START = 32'hF0000000,
parameter logic [31:0] DM_REGION_END = 32'hF0003FFF
)
(
input logic clk,
Expand Down Expand Up @@ -232,7 +234,9 @@ module cv32e40x_if_stage import cv32e40x_pkg::*;
.CORE_RESP_TYPE ( inst_resp_t ),
.BUS_RESP_TYPE ( obi_inst_resp_t ),
.PMA_NUM_REGIONS ( PMA_NUM_REGIONS ),
.PMA_CFG ( PMA_CFG )
.PMA_CFG ( PMA_CFG ),
.DM_REGION_START ( DM_REGION_START ),
.DM_REGION_END ( DM_REGION_END )
)
mpu_i
(
Expand Down
8 changes: 6 additions & 2 deletions rtl/cv32e40x_load_store_unit.sv
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Expand Up @@ -32,7 +32,9 @@ module cv32e40x_load_store_unit import cv32e40x_pkg::*;
parameter int X_ID_WIDTH = 4,
parameter int PMA_NUM_REGIONS = 0,
parameter pma_cfg_t PMA_CFG[PMA_NUM_REGIONS-1:0] = '{default:PMA_R_DEFAULT},
parameter int DBG_NUM_TRIGGERS = 1
parameter int DBG_NUM_TRIGGERS = 1,
parameter logic [31:0] DM_REGION_START = 32'hF0000000,
parameter logic [31:0] DM_REGION_END = 32'hF0003FFF
)
(
input logic clk,
Expand Down Expand Up @@ -720,7 +722,9 @@ module cv32e40x_load_store_unit import cv32e40x_pkg::*;
.BUS_RESP_TYPE ( obi_data_resp_t ),
.CORE_REQ_TYPE ( obi_data_req_t ),
.PMA_NUM_REGIONS ( PMA_NUM_REGIONS ),
.PMA_CFG ( PMA_CFG )
.PMA_CFG ( PMA_CFG ),
.DM_REGION_START ( DM_REGION_START ),
.DM_REGION_END ( DM_REGION_END )
)
mpu_i
(
Expand Down
31 changes: 19 additions & 12 deletions rtl/cv32e40x_mpu.sv
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Expand Up @@ -31,7 +31,9 @@ module cv32e40x_mpu import cv32e40x_pkg::*;
parameter type CORE_RESP_TYPE = inst_resp_t,
parameter type BUS_RESP_TYPE = obi_inst_resp_t,
parameter int PMA_NUM_REGIONS = 0,
parameter pma_cfg_t PMA_CFG[PMA_NUM_REGIONS-1:0] = '{default:PMA_R_DEFAULT})
parameter pma_cfg_t PMA_CFG[PMA_NUM_REGIONS-1:0] = '{default:PMA_R_DEFAULT},
parameter logic [31:0] DM_REGION_START = 32'hF0000000,
parameter logic [31:0] DM_REGION_END = 32'hF0003FFF)
(
input logic clk,
input logic rst_n,
Expand Down Expand Up @@ -82,6 +84,10 @@ module cv32e40x_mpu import cv32e40x_pkg::*;
logic instr_fetch_access;
logic load_access;
logic wpt_match;
logic core_trans_debug_region;

// Detect a debug mode transaction to the Debug Module region
assign core_trans_debug_region = (core_trans_i.addr >= DM_REGION_START) && (core_trans_i.addr <= DM_REGION_END) && core_trans_i.dbg;

// FSM that will "consume" transfers failing PMA checks.
// Upon failing checks, this FSM will prevent the transfer from going out on the bus
Expand Down Expand Up @@ -185,20 +191,21 @@ module cv32e40x_mpu import cv32e40x_pkg::*;
// PMA - Physical Memory Attribution
cv32e40x_pma
#(
.A_EXT ( A_EXT ),
.PMA_NUM_REGIONS ( PMA_NUM_REGIONS ),
.PMA_CFG ( PMA_CFG )
.A_EXT ( A_EXT ),
.PMA_NUM_REGIONS ( PMA_NUM_REGIONS ),
.PMA_CFG ( PMA_CFG )
)
pma_i
(
.trans_addr_i ( core_trans_i.addr ),
.instr_fetch_access_i ( instr_fetch_access ),
.atomic_access_i ( atomic_access_i ),
.misaligned_access_i ( misaligned_access_i ),
.load_access_i ( load_access ),
.pma_err_o ( pma_err ),
.pma_bufferable_o ( bus_trans_bufferable ),
.pma_cacheable_o ( bus_trans_cacheable )
.trans_addr_i ( core_trans_i.addr ),
.trans_debug_region_i ( core_trans_debug_region ),
.instr_fetch_access_i ( instr_fetch_access ),
.atomic_access_i ( atomic_access_i ),
.misaligned_access_i ( misaligned_access_i ),
.load_access_i ( load_access ),
.pma_err_o ( pma_err ),
.pma_bufferable_o ( bus_trans_bufferable ),
.pma_cacheable_o ( bus_trans_cacheable )
);

assign mpu_err = pma_err;
Expand Down
42 changes: 32 additions & 10 deletions rtl/cv32e40x_pma.sv
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Original file line number Diff line number Diff line change
@@ -1,13 +1,13 @@
// Copyright 2021 Silicon Labs, Inc.
//
//
// This file, and derivatives thereof are licensed under the
// Solderpad License, Version 2.0 (the "License");
// Use of this file means you agree to the terms and conditions
// of the license and are in full compliance with the License.
// You may obtain a copy of the License at
//
//
// https://solderpad.org/licenses/SHL-2.0/
//
//
// Unless required by applicable law or agreed to in writing, software
// and hardware implementations thereof
// distributed under the License is distributed on an "AS IS" BASIS,
Expand All @@ -24,13 +24,14 @@
////////////////////////////////////////////////////////////////////////////////

module cv32e40x_pma import cv32e40x_pkg::*;
#(
#(
parameter bit A_EXT = 0,
parameter int PMA_NUM_REGIONS = 0,
parameter pma_cfg_t PMA_CFG[PMA_NUM_REGIONS-1:0] = '{default:PMA_R_DEFAULT}
)
(
input logic [31:0] trans_addr_i,
input logic trans_debug_region_i, // Transaction address is inside the debug redion
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redion -> region

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Fixed

input logic instr_fetch_access_i, // Indicate that ongoing access is an instruction fetch
input logic atomic_access_i, // Indicate that ongoing access is atomic
input logic misaligned_access_i, // Indicate that ongoing access is part of a misaligned access
Expand All @@ -39,9 +40,18 @@ module cv32e40x_pma import cv32e40x_pkg::*;
output logic pma_bufferable_o,
output logic pma_cacheable_o
);

parameter PMA_ADDR_LSB = 0; // TODO:OE experiment and see if this makes a difference


// Attributes for accessing the DM (DM_REGION_START:DM_REGION_END) in debug mode
localparam pma_cfg_t PMA_DBG = '{word_addr_low : '0, // not used
word_addr_high : '0, // not used
main : 1'b1,
bufferable : 1'b0,
cacheable : 1'b0,
atomic : 1'b0};


pma_cfg_t pma_cfg;
logic [31:0] word_addr;
logic pma_cfg_atomic;
Expand All @@ -55,6 +65,13 @@ module cv32e40x_pma import cv32e40x_pkg::*;
// PMA is deconfigured
assign pma_cfg = NO_PMA_R_DEFAULT;

always_comb begin
// When core is in debug mode, use PMA_DBG as attributes for the DM range
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When core is in debug mode, -> Debug mode transactions within the Debug Module region

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Fixed

if (trans_debug_region_i) begin
pma_cfg = PMA_DBG;
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Multiple assignment together with line 66

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Fixed

end
end

end
else begin: pma

Expand All @@ -65,11 +82,16 @@ module cv32e40x_pma import cv32e40x_pkg::*;
pma_cfg = PMA_R_DEFAULT;

for(int i = PMA_NUM_REGIONS-1; i >= 0; i--) begin
if((word_addr[31:PMA_ADDR_LSB] >= PMA_CFG[i].word_addr_low[31:PMA_ADDR_LSB]) &&
if((word_addr[31:PMA_ADDR_LSB] >= PMA_CFG[i].word_addr_low[31:PMA_ADDR_LSB]) &&
(word_addr[31:PMA_ADDR_LSB] < PMA_CFG[i].word_addr_high[31:PMA_ADDR_LSB])) begin
pma_cfg = PMA_CFG[i];
end
end

// When core is in debug mode, use PMA_DBG as attributes for the DM range
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When core is in debug mode, -> Debug mode transactions within the Debug Module region

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Fixed

if (trans_debug_region_i) begin
pma_cfg = PMA_DBG;
end
end
end

Expand All @@ -84,10 +106,10 @@ module cv32e40x_pma import cv32e40x_pkg::*;
assign pma_cfg_atomic = 1'b0;
end
endgenerate

// Check transaction based on PMA region config
always_comb begin

pma_err_o = 1'b0;

// Check for atomic access
Expand All @@ -110,5 +132,5 @@ module cv32e40x_pma import cv32e40x_pkg::*;
// Instruction fetches, atomic operations and loads are never classified as bufferable
assign pma_bufferable_o = pma_cfg.bufferable && !instr_fetch_access_i && !atomic_access_i && !load_access_i;
assign pma_cacheable_o = pma_cfg.cacheable;

endmodule
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