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Hooked up mnxti to RVFI. #657

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Merged
merged 1 commit into from
Aug 30, 2022
Merged

Hooked up mnxti to RVFI. #657

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4 changes: 2 additions & 2 deletions bhv/cv32e40x_wrapper.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -524,8 +524,8 @@ endgenerate
.csr_mip_n_i ( core_i.cs_registers_i.mip_n ),
.csr_mip_q_i ( core_i.cs_registers_i.mip_rdata ),
.csr_mip_we_i ( core_i.cs_registers_i.mip_we ),
.csr_mnxti_n_i ( '0/*todo: handle mnxti and rvfi*/ ),
.csr_mnxti_q_i ( '0/*todo: handle mnxti and rvfi*/ ),
.csr_mnxti_n_i ( core_i.cs_registers_i.mnxti_n ),
.csr_mnxti_q_i ( core_i.cs_registers_i.mnxti_rdata ),
.csr_mnxti_we_i ( core_i.cs_registers_i.mnxti_we ),
.csr_mintstatus_n_i ( core_i.cs_registers_i.mintstatus_n ),
.csr_mintstatus_q_i ( core_i.cs_registers_i.mintstatus_rdata ),
Expand Down
19 changes: 11 additions & 8 deletions rtl/cv32e40x_cs_registers.sv
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Expand Up @@ -193,7 +193,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
mtvt_t mtvt_q, mtvt_n, mtvt_rdata;
logic mtvt_we;

logic [31:0] mnxti_rdata; // No CSR module instance
logic [31:0] mnxti_n, mnxti_rdata; // No CSR module instance
logic mnxti_we;

mintstatus_t mintstatus_q, mintstatus_n, mintstatus_rdata;
Expand Down Expand Up @@ -376,7 +376,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
// The data read here is what will be used in the read-modify-write portion of the CSR access.
// For mnxti, this is actually mstatus. The value written back to the GPR will be the address of
// the function pointer to the interrupt handler. This is muxed in the WB stage.
csr_rdata_int = mnxti_rdata;
csr_rdata_int = mstatus_rdata;
csr_mnxti_read_o = 1'b1;
end else begin
csr_rdata_int = '0;
Expand Down Expand Up @@ -923,7 +923,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
// with a higher level. The valid below will be high also for the cases where
// no side effects occur.
clic_pa_valid_o = csr_en_gated && (csr_waddr == CSR_MNXTI);
clic_pa_o = mnxti_irq_pending_i ? {mtvt_addr_o, mnxti_irq_id_i, 2'b00} : 32'h00000000;
clic_pa_o = mnxti_rdata;
end else begin
clic_pa_valid_o = 1'b0;
clic_pa_o = '0;
Expand Down Expand Up @@ -1020,6 +1020,9 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
endcase
end

// Mirroring mstatus_n to mnxti_n for RVFI
assign mnxti_n = mstatus_n;

// CSR operation logic
// Using ex_wb_pipe_i.rf_wdata for read-modify-write since CSR was read in EX, written in WB
always_comb
Expand Down Expand Up @@ -1340,10 +1343,10 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
assign mclicbase_rdata = mclicbase_q;
assign mie_rdata = mie_q;

// mnxti_rdata will be used in the read-modify-write portion of the CSR access.
// For mnxti, this is actually mstatus. The value written back to the GPR will be
// the address of the function pointer to the interrupt handler.
assign mnxti_rdata = mstatus_rdata;
// mnxti_rdata breaks the regular convension for CSRs. The read data used for read-modify-write is the mstatus_rdata,
// while the value read and written back to the GPR is a pointer address if an interrupt is pending, or zero
// if no interrupt is pending.
assign mnxti_rdata = mnxti_irq_pending_i ? {mtvt_addr_o, mnxti_irq_id_i, 2'b00} : 32'h00000000;

assign mip_rdata = mip_i;
assign misa_rdata = MISA_VALUE;
Expand Down Expand Up @@ -1738,6 +1741,6 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
// Some signals are unused on purpose (typically they are used by RVFI code). Use them here for easier LINT waiving.

assign unused_signals = tselect_we | tinfo_we | tcontrol_we | mstatush_we | misa_we | mip_we | mvendorid_we |
marchid_we | mimpid_we | mhartid_we | mconfigptr_we | mtval_we;
marchid_we | mimpid_we | mhartid_we | mconfigptr_we | mtval_we | (|mnxti_n);

endmodule