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ERROR: PCI CFG write to enable ROM access failed #4

@AreYouLoco

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@AreYouLoco

Hi,

First of all thank you for that tool. I was sure someone made that on github.

My controller works on one kernel (stock 4.19.x) but not on other (backported mainline 5.3.x ). Nevermind.

I tried to check if it's firmware fault first. So I get update 2.0.2.6 (http://www.station-drivers.com/index.php?option=com_remository&Itemid=352&func=download&id=1348&chk=bd3c73072d43c63d1d5857cb9e99c919) from da Internets and extracted UPDATE.mem from there and tried to check version and possibly update with your tool.

Seems like I have latest one looking at the major version but maybe there is some small revision difference. But your tool doesn't allow me to backup anyway. Here is what I get:

user@linux:~/code/upd72020x-load$ sudo ./upd72020x-load -r -b 0x05 -d 0x00 -f 0x0 -o ./firmware_bak.bin
Doing the reading
bus = 5 
dev = 0 
fct = 0 
fname = ./firmware_bak.bin 
got firmware version: 202609
EEPROM installed
got rom_info: 19d207f
got rom_config: 0
setting rom_config: 700
ERROR: PCI CFG write to enable ROM access failed
ERROR: cant enable access to ROM 
 ======> FAILED

Generated file is empty! Not a surprise since it didn't work.

user@linux:~/code/upd72020x-load$ du -hs firmware_bak.bin 
0	firmware_bak.bin

Some background: Debian 10 4.19.0-6-amd64 @ Thinkpad T420

user@linux:~/code/upd72020x-load$ sudo lspci -vv -nn -s 05:00.0 -G -M -H 1 -xxxx -k -t
Decided to use intel-conf1
Mapping bus 05
Discovered device 05:00.0
05:00.0 USB controller [0c03]: Renesas Technology Corp. uPD720202 USB 3.0 Host Controller [1912:0015] (rev 02) (prog-if 30 [XHCI])
Using cache /root/.pciids-cache
Initializing UDEV HWDB
	Subsystem: Renesas Technology Corp. uPD720202 USB 3.0 Host Controller [1912:0015]
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 0
	Region 0: Memory at 91c00000 (64-bit, non-prefetchable)
	Capabilities: [50] Power Management version 3
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [70] MSI: Enable- Count=1/8 Maskable- 64bit+
		Address: 0000000000000000  Data: 0000
	Capabilities: [90] MSI-X: Enable+ Count=8 Masked-
		Vector table: BAR=0 offset=00001000
		PBA: BAR=0 offset=00001080
	Capabilities: [a0] Express (v2) Endpoint, MSI 00
		DevCap:	MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited
			ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0.000W
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+
			MaxPayload 128 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend-
		LnkCap:	Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <4us, L1 unlimited
			ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp-
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
		DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR+, OBFF Not Supported
		DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
		LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
			 Compliance De-emphasis: -6dB
		LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
			 EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
00: 12 19 15 00 06 04 10 00 02 30 03 0c 10 00 00 00
10: 04 00 c0 91 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 12 19 15 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 00 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 70 c3 c9 08 00 00 00 00 00 00 00 00 00 00 00
60: 30 20 00 00 00 00 00 00 00 00 00 00 09 26 20 00
70: 05 90 86 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 11 a0 07 80 00 10 00 00 80 10 00 00 00 00 00 00
a0: 10 00 02 00 c0 8f 00 00 00 28 19 00 12 ec 07 00
b0: 40 00 12 10 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 10 08 00 00 00 00 00 00 00 00 00 00
d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 03 00 00 00 01 05 7f 20 9d 01
f0: 00 07 00 00 00 00 01 80 4d 4f 52 53 00 00 00 00

Summary of buses:
05: Secondary host bus (?)

Any thoughts what might be wrong?

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