An attempt to model the SID opamp transfer functions
12V 12V
T T
| |
| |
| +------o
| | |
| | ||--+
| +--||
| ||--+
||--+ |
Vi -----|| o---o----- Vo
||--+ | |
| Vx ||--+ |
o-------|| |
| ||--+ |
||--+ | |
+--|| | |
| ||--+ | |
| | | |
| | | |
| V V |
| |
| GND GND |
| |
+----------------------+
Vi - input voltage
Vo - output voltage
The schematics above are laid out to show that the "op-amp" logically consists of two building blocks; an enhancement load NMOS inverter (on the right hand side of the schematics) with a common drain input stage biased by the output voltage (on the left hand side of the schematics).
- M1a (top left) ~ 80/20
- M2a (bottom left) ~ 25/70
- M1b (top right) ~ 40/20
- M2b (bottom right) ~ 650/20
Assuming uCox = 20uA/V² and Vt = 1.31V
unfortunately this is quite off from the measured values.
Open questions:
- are all the transistors enhancement-mode?
- do all the transistors have the same Vt?