Engineering student at Harvey Mudd College;
Clay-Wolkin VLSI Research Fellow
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  cvwcvw PublicForked from openhwgroup/cvw CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache… SystemVerilog 1 
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  cvw-arch-verifcvw-arch-verif PublicForked from openhwgroup/cvw-arch-verif The purpose of the repo is to support CORE-V Wally architectural verification SystemVerilog 
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