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.gitignore
.gitignore
 
 
Control_Unit.v
Control_Unit.v
 
 
Inst_ROM.v
Inst_ROM.v
 
 
Inst_ROM2.v
Inst_ROM2.v
 
 
Inst_ROM3.v
Inst_ROM3.v
 
 
PPCPU.v
PPCPU.v
 
 
PPCPU_tb.v
PPCPU_tb.v
 
 
README.md
README.md
 
 
Regfile.v
Regfile.v
 
 
add32.v
add32.v
 
 
alu.v
alu.v
 
 
dff32.v
dff32.v
 
 
exe_mem_register.v
exe_mem_register.v
 
 
exe_mem_register_withWZ.v
exe_mem_register_withWZ.v
 
 
execute.v
execute.v
 
 
id_exe_register.v
id_exe_register.v
 
 
instruction_decode.v
instruction_decode.v
 
 
instruction_fetch.v
instruction_fetch.v
 
 
instruction_register.v
instruction_register.v
 
 
mem_wb_register.v
mem_wb_register.v
 
 
memory.v
memory.v
 
 
mux1_2_1.v
mux1_2_1.v
 
 
mux32_2_1.v
mux32_2_1.v
 
 
mux32_4_1.v
mux32_4_1.v
 
 
mux5_2_1.v
mux5_2_1.v
 
 
program_counter.v
program_counter.v
 
 
write_back.v
write_back.v
 
 

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Mips CPU with Pipeline

Verilog Code to simulate MIPS CPU with pipeline.

Developed as the expriment project for Computer Architecture in UESTC

Instructions

  • add
  • and
  • or
  • xor
  • srl
  • sll
  • addi
  • andi
  • ori
  • xori
  • load
  • store
  • beq
  • bne
  • jump

Implementation

  • Data hazard
  • Control hazard

How to Run

  1. Clone this repo

    https://github.com/neverfelly/mips-pipelinedcpu.git
cd mips-pipelindcpu

  2. Compile all files

    iverilog -o main *.v

  3. Run the compiled binary

    vvp -n main -lxt2

  4. Verify wave graph

    gtkwave ppcpu.vcd

Requriments

Credits

Keqiang Li

About

UESTC Computer Architecture experiment

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Readme
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