Absolute value

lib/src/modules/gates.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2021-2023 Intel Corporation
+// Copyright (C) 2021-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // gates.dart

lib/src/signals/logic.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2021-2023 Intel Corporation
+// Copyright (C) 2021-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // logic.dart
@@ -638,7 +638,16 @@ class Logic {
     ].swizzle();
   }
 
-  /// Returns a new [Logic] with width [newWidth] where new bits added are sign
+  /// Calculates the absolute value of a signal, assuming that the
+  /// number is a two's complement.
+  Logic abs() {
+    if (width == 0) {
+      return this;
+    }
+    return mux(this[-1], ~this + 1, this);
+  }
+
+  /// Returns a new [Logic] width width [newWidth] where new bits added are sign
   /// bits as the most significant bits.  The sign is determined using two's
   /// complement, so it takes the most significant bit of the original signal
   /// and extends with that.

lib/src/signals/logic_structure.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023 Intel Corporation
+// Copyright (C) 2023-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // logic_structure.dart
@@ -483,6 +483,9 @@ class LogicStructure implements Logic {
   @override
   Logic get reversed => packed.reversed;
 
+  @override
+  Logic abs() => packed.abs();
+
   @override
   Logic signExtend(int newWidth) => packed.signExtend(newWidth);
 

lib/src/values/logic_value.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2021-2023 Intel Corporation
+// Copyright (C) 2021-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // logic_values.dart
@@ -862,6 +862,20 @@ abstract class LogicValue implements Comparable<LogicValue> {
     return op(this, other);
   }
 
+  /// Calculates the absolute value, assuming that the
+  /// number is a two's complement.
+  LogicValue abs() {
+    if (width == 0) {
+      return this;
+    }
+    if (!this[-1].isValid) {
+      return LogicValue.filled(width, LogicValue.x);
+    }
+    return this[-1] == LogicValue.one
+        ? ~this + LogicValue.ofInt(1, width)
+        : this;
+  }
+
   /// Unary AND operation.
   ///
   /// Returns `1` iff all bits are `1`.

test/extend_test.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2022-2023 Intel Corporation
+// Copyright (C) 2022-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // extend_test.dart

test/gate_test.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2021-2023 Intel Corporation
+// Copyright (C) 2021-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // gate_test.dart
@@ -55,6 +55,16 @@ class UnaryGateTestModule extends Module {
   }
 }
 
+class Absolute extends Module {
+  Absolute(Logic a) : super(name: 'absolute') {
+    a = addInput('a', a, width: a.width);
+
+    final y = addOutput('y', width: a.width);
+
+    y <= a.abs();
+  }
+}
+
 class ShiftTestModule extends Module {
   dynamic constant; // int or BigInt
 
@@ -410,6 +420,20 @@ void main() {
       expect(simResult, equals(true));
     });
 
+    test('absolute', () async {
+      final mod = Absolute(Logic(width: 4));
+      await mod.build();
+      final vectors = [
+        Vector({'a': bin('1111')}, {'y': bin('0001')}),
+        Vector({'a': bin('0110')}, {'y': bin('0110')}),
+        Vector({'a': bin('0010')}, {'y': bin('0010')}),
+        Vector({'a': bin('1011')}, {'y': bin('0101')}),
+      ];
+      await SimCompare.checkFunctionalVector(mod, vectors);
+      final simResult = SimCompare.iverilogVector(mod, vectors);
+      expect(simResult, equals(true));
+    });
+
     test('Mux bus', () async {
       final mod = MuxWrapper(Logic(), Logic(width: 8), Logic(width: 8));
       await mod.build();

test/logic_value_test.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2021-2023 Intel Corporation
+// Copyright (C) 2021-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // logic_value_test.dart
@@ -1163,6 +1163,24 @@ void main() {
           equals(LogicValue.filled(4, LogicValue.x)));
     });
 
+    test('absolute', () {
+      expect(
+          // test of positive value
+          LogicValue.ofInt(2, 32).abs(),
+          equals(LogicValue.ofInt(2, 32)));
+      expect(
+          // test of negative value
+          LogicValue.ofInt(-7, 32).abs(),
+          equals(LogicValue.ofInt(7, 32)));
+      expect(
+          // test of zero width 
+          LogicValue.filled(0, LogicValue.zero).abs(),
+          equals(LogicValue.filled(0, LogicValue.zero)));
+      expect(
+          //test string
+          LogicValue.ofString('000010').abs(),
+          equals(LogicValue.ofString('000010')));
+    });
     test('addsub', () {
       expect(
           // + normal