Add an easier way to name important generated signals

[mkorbel1]

Motivation

Sometimes the result of some hardware is important and needs to be named so that it can be visible in the generated output (e.g. SystemVerilog). One way to do that is to first construct a named signal, then assign it to the result of that operation. For example:

final myImportantSignal = Logic(name: 'my_sig')..gets(a & b | c);

This is a little verbose and the cascade notation can be intimidating/unintuitive to people new to Dart/ROHD. An improved API for the same thing could look something like:

final myImportantSignal = (a & b | c).named('my_sig');

Desired solution

Add a named function that provides an ability to construct a new Logic clone with a specified name (and Naming). Perhaps adding a clone function to Logic (as already exists on LogicStructure) would be a good implementation approach, then named could just wrap clone with an even simpler API.

Alternatives considered

No response

Additional details

No response

[mkorbel1]

Fixed in #550