This repository provides a shell template for SAKURA-X board. Vivado 2023.2 was used to verify the design.

SAKURA-X is composed of two FPGAs, Spartan-6 and Kintex-7. Once the Spartan-6 FPGA is configured with the provided design, you don't need to reconfigure it. The Spartan-6 FPGA is responsible for bridging the Kinex-7 FPGA and the host PC.

The Kintex-7 FPGA is designed to implement your cryptographic module. The shell template provides an AXI4 interface to connect your IP. So, you can easily implement your IP, which has an AXI4 interface, and communicate with the host PC via USB. Thanks to the AXI4 interface, a multi-clock design is also available. The template optionally includes a Memory Interface Generator (MIG) IP to use DDR memory.

sakura-x-shell-ctrl includes ISE project for Spartan-6 FPGA. In addition, pre-built bitstream file and MCS file are included in that directory. The pre-built design is clocked at 20 MHz. Please see Configuration with iMPACT to configure the Spartan-6 FPGA.

First, clone this repository.

git clone --recursive https://github.com/hal-lab-u-tokyo/sakura-x-shell.git
cd sakura-x-shell

The following command will launch Vivado and create a project

vivado -source <path to this repo>/vivado/init-shell-project.tcl

For more details, see doc/create_project.md.

We also provide driver software to communicate with SAKURA-X via USB. It is included in our ChipWhisperer Plugin. Thus, it is compatible with ChipWhisperer, which is a popular open-source tool for side-channel analysis.

To communicate with your cryptographic module on SAKURA-X, you have only to implement a Python class derived from a base class provided in the plugin. The base class already implements common functions to communicate with SAKURA-X controller part. For more details, see here

This repository contains cryptographic module examples as a submodule. Detailed information about each example is available in the submodule repository.

examples directory includes scripts to create block designs with the cryptographic modules.

After creating a project with the template, as described above, you can create a block design by running the following command in the Vivado Tcl console.

source <path to this repo>/examples/aes128_aist_rtl/create_bd.tcl

To run the encryption with the design, please use SakuraXShellExampleAES128BitRTL class in the ChipWhisperer Plugin.

Other RTL implementations of AES 128-bit encryption are available in examples/aes128_googlevault_rtl and examples/aes128_rsm_rtl directories. For aes128_rsm_rtl, you need to generate mask tables by running a setup script setup_ip.sh in the directory. Detailed instructions are also available in the submodule repository. The same class SakuraXShellExampleAES128BitRTL can be used to run the encryption with the design but don't forget to set implementation="google" or implementation="rsm" argument when con method is called.

First, you need to create an IP package from the HLS source code. In examples/aes128_hls directory, a script to create an IP package is available.

cd examples/aes128_hls
sh create_hls_ip.sh

It will create an IP package in examples/aes128_hls/hls_sakura-x_aes_enc. The target frequency is set to 20 MHz in the script, but you can change it.

After creating a project with the template, as described above, you can create a block design by running the following command in the Vivado Tcl console.

source <path to this repo>/examples/aes128_hls/create_bd.tcl

To run the encryption with the design, please use SakuraXShellExampleAES128BitHLS class in the ChipWhisperer Plugin.

Another HLS implementation of AES 128-bit encryption is available in examples/aes128_hls_rsm, which is a protected version of the AES encryption by RSM masking scheme. IP package creation and block design creation are the same as the above. But don't forget to set implementation="rsm" argument when con method is called.

32bit RISC-V core, VexRiscv, is also available on SAKURA-X.

See VexRiscv_SAKURA-X repo for more details.

This repository is licensed under MIT License, see LICENSE for more information.

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