Update layout and routing

[Tejasgarg]

This is a work in progress, and I will be updating this with the complete routing.

This PR aims to update the layout and routing for the board with updates from the Oscilloscope front end and power circuitry.

• fixes: Update layouting and routing  #49
• fixes: Fix ESP32 Antenna #35

Summary by Sourcery

Update PSLab mini PCB layout and routing, synchronise schematics with oscilloscope frontend and power circuitry updates, and add the 2450AT18D0100001E component’s 3D model and footprint.

Enhancements:

• Revise PCB layout and routing for the PSLab mini board to integrate frontend and power circuit changes.
• Update schematic and symbol files to reflect oscilloscope frontend and power design updates.
• Add 3D model and footprint for the 2450AT18D0100001E component to the design libraries.

[sourcery-ai]

Reviewer's guide (collapsed on small PRs)

Reviewer's Guide

Integrates updated Oscilloscope front end and power circuitry by refreshing PCB layout, schematic routing, and KiCad project files

File-Level Changes

Change	Details	Files
Refreshed PCB layout and 3D models for new front-end component	Revised analog signal trace routing Adjusted component placement for signal integrity Added 3D model file for ADC component	schematic/pslab-mini.kicad_pcb schematic/3DModels/2450AT18D0100001E.stp schematic/pslab-mini.pretty/2450AT18D0100001E.kicad_mod
Updated schematic symbols and net routing for power circuitry	Modified symbols for power components Rerouted power nets and updated labels	schematic/pslab-mini.kicad_sch schematic/pslab-mini.kicad_sym
Refreshed KiCad project configuration	Updated project file settings and version Cleaned up outdated file references	schematic/pslab-mini.kicad_pro

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Hey there - I've reviewed your changes and they look great!

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Hey there - I've reviewed your changes and they look great!

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[CloudyPadmal]

Why are there several resistors such as R25, R22 etc are in 0805 package instead of 0603? Is that intentional or by mistake?

Also the variable capacitors have rather a wide courtyard. Make it smaller similar to stock footprints in KiCAD and place the capacitors (fixed+variable) close to each other.

I see some ground vias from components exit the pads diagonally, while some straight out. Is there a reason for the difference routing?

Did you check the impedance of the oscilloscope traces are matched to 50 Ohms? I see that almost all the traces are 0.2 mm.

The orientation of switch labels POWER and RESET are different from one another. The labels aren't even center aligned with the switches. Please focus on the aesthetics and fix those issues.

[Tejasgarg]

Why are there several resistors such as R25, R22 etc are in 0805 package instead of 0603? Is that intentional or by mistake?

Yes, I went with the 0805 package, as currently there is only a 0805-based 6k resistor available on LCSC.

Also the variable capacitors have rather a wide courtyard. Make it smaller similar to stock footprints in KiCAD and place the capacitors (fixed+variable) close to each other.

Ok! I will update this in the schematic.

I see some ground vias from components exit the pads diagonally, while some straight out. Is there a reason for the difference routing?

I did this mostly based on the spacing around the component, and in order to avoid the silkscreen getting cut. However, I will work on the design a bit more and update this to ensure more consistency in this regard throughout the design.

Did you check the impedance of the oscilloscope traces are matched to 50 Ohms? I see that almost all the traces are 0.2 mm.

Oh, thanks for pointing this out!
I will change it to 0.35mm routing to match the 50 ohm impedance for the oscilloscope track.

The orientation of switch labels POWER and RESET are different from one another. The labels aren't even center aligned with the switches. Please focus on the aesthetics and fix those issues.

Ok! I will update these in the layout.

Other notable changes in this commit are
The antenna is now changed from the 2450AT18A100 to 2450AT18D0100.
Here are the datasheets for both:

2450AT18A100: https://www.lcsc.com/datasheet/C89334.pdf
2450AT18D0100: https://www.lcsc.com/datasheet/C2917718.pdf
I have changed this because the 2450AT18A100 is designed to be placed at the corner of the board, whereas the 2450AT18D0100 seems to be more appropriate for our use case, where the antenna is placed at the center of the board edge.
The antenna trace is now a 0.35mm, impedance-matched 50 ohm line. Also, the antenna now has a 6mmX4mm ground plane removed beneath it, as recommended by the datasheet

• fixes: Fix ESP32 Antenna #35

Also, I have updated the pin assignment of the main MCU for cleaner routing and increased the number of analog GPIO.
Since removing the PGA, quite a few ADC-connected pins have been freed up.
So, I have increased the number of GPIO with analog capability from 4->6
Now,
GPIO0-GPIO5 have analog capability.

[CloudyPadmal]

Regarding the 6k resistors only being available in 0805 indicates that there will be trouble sourcing them.

Please replace those resistors with a more commonly available resistor (preferably with a closer but different resistor value)

[Tejasgarg]

Regarding the 6k resistors only being available in 0805 indicates that there will be trouble sourcing them.

Please replace those resistors with a more commonly available resistor (preferably with a closer but different resistor value)

Hi @CloudyPadmal,
Yeah, I agree.
However, this is a problem that I did try to resolve while making the schematic but it leads to another problem.

As discussed in this issue, we want the total impedance to be close to 3.2k:
#21 (comment)

And we want the ratio between the resistors to be 3:5 to achieve the required gain for our output to be in the range 150mV-3.15V

So, I searched using these parameters
The values that we could start with are
5.1k - 8.5k (total impedance approximately 3.1875k ohm)
However, 8.5k is not available

The common values between 5.1k-7k are:
5.11k
5.17k
5.23k
5.36k
5.49k --------
5.56k
5.6k
5.62k
5.76k --------- these 5 resistors are divisible by 3 and lead to simpler calculations
5.8k
5.9k
5.97k ---------
6k
6.04k
6.19k
6.2k
6.34k
6.49k
6.57k ---------
6.65k
6.8k
6.81k ---------
6.89k

However, none of the resistor pairs are available
5.49k -> 9.15k(not available)
5.76k -> 9.6k(not available)
5.97k -> 9.95(not available)
6.57k -> 10.95(not available)
6.81k -> 11.35(not available)

This is the reason I went with the 6k resistor

However, Another Idea I have is that we could maybe use 2 X 3k resistors in series.
As that is a very common value.
@CloudyPadmal @bessman thoughts?

[Tejasgarg]

Oh, on searching for it again
6.12k and 10.2k resistors are available and close to the previous values.
This could also be a viable option

Sorry, my bad, 6.12k is in fact not available

[bessman]

Regarding the layout, it mostly looks good except the ADC pin caps (C40/C41). They must be as close as possible to the actual pin on the MCU. The op-amp output resistors (R28/R29) should be kept close to the op-amp; the trace between R28/29 and C40/41 can be long-ish.

[bessman]

The op-amp rails should be decoupled with 100 nF close to the pins (3.3V and -2V). C29 is too far away; it should be within a few mm.

[bessman]

However, Another Idea I have is that we could maybe use 2 X 3k resistors in series.

Should be fine. Make sure to keep them very close together in that case, especially in the op-amp feedback network. The op-amp inputs are less critical; we can afford mode space between the 3ks there.

[bessman]

The GDTs' ground should be connected directly to the BNC shells, not via signal ground vias.

Edit: Or even better, keep the vias but also add a wide path directly to the nearest BNC ground leg.

[CloudyPadmal]

There is currently a single ground layer. We need to separate the two analog and digital ground planes. Please fix that too.

[bessman]

Does the old hardware have separate analog and digital ground planes, @CloudyPadmal? Why do they need to be separate?

[CloudyPadmal]

That is to reduce digital switching transient ground currents from contaminating the analog circuitry.

I'm not 100% sure if the old hardware has it, it might.

[Tejasgarg]

That is to reduce digital switching transient ground currents from contaminating the analog circuitry.

I'm not 100% sure if the old hardware has it, it might.

Hey, @CloudyPadmal
I was thinking of how we can implement separate ground planes for digital and analog circuitry.
However, with our design, this seems quite complicated as many analog and digital components are quite closely placed.
Here is the rough segregations for the analog and digital parts, what are your thoughts on how I should implement seperate ground planes.
Also, let me know if I have missed anything or wrongly marked any component
Thanks!

J5 Connector:

Complete Board

[CloudyPadmal]

Hi @Tejasgarg

The most sensitive analog circuit that we need to protect from transients is at the top right. So, we can have a ground pour that covers that region you have marked in a yellow square and have a small connection or two to connect with the rest of the ground plane.

What do you think?

[Tejasgarg]

Yes, that sounds like a good idea and will help us isolate the oscilloscope front end from transients.
Somewhat like this, right?
Rough Image:

[CloudyPadmal]

Yes, this looks correct

[Tejasgarg]

The op-amp rails should be decoupled with 100 nF close to the pins (3.3V and -2V). C29 is too far away; it should be within a few mm.

Hey, @bessman!
I have a small question here, C29 is a decoupling capacitor for the MCU and is placed about 1.5mm from the MCU.
Am I overlooking something here?

[CloudyPadmal]

Always place the capacitor closer to the IC pins, not the resistor.

The two channels are almost identical. Why not make the layout symmetric?

[bessman]

I have a small question here, C29 is a decoupling capacitor for the MCU and is placed about 1.5mm from the MCU.
Am I overlooking something here?

The location of C29 is fine for the MCU. The op-amps in the scope input need their own decoupling caps close to their power rails.

[Tejasgarg]

Always place the capacitor closer to the IC pins, not the resistor.

Ok! I will keep this in mind. Thanks!

The two channels are almost identical. Why not make the layout symmetric?

Yes, as pointed out by @bessman as well during the meet.
I will be updating the layout to make both channels more symmetric.

[Tejasgarg]

I have a small question here, C29 is a decoupling capacitor for the MCU and is placed about 1.5mm from the MCU.
Am I overlooking something here?

The location of C29 is fine for the MCU. The op-amps in the scope input need their own decoupling caps close to their power rails.

Ok! understood, thanks :)
I will add 100nF capacitors to the power rails for the op-amps.

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[Tejasgarg]

Why are there several resistors such as R25, R22 etc are in 0805 package instead of 0603? Is that intentional or by mistake?

This is switched to 2X 3k resistors in series, which are 0402 package with 0.1% tolerance.

Also the variable capacitors have rather a wide courtyard. Make it smaller similar to stock footprints in KiCAD and place the capacitors (fixed+variable) close to each other.

This is fixed now!

I see some ground vias from components exit the pads diagonally, while some straight out. Is there a reason for the difference routing?

I have gone over the entire schematic and tried to make it so that almost all the ground pads are exited diagonally

Did you check the impedance of the oscilloscope traces are matched to 50 Ohms? I see that almost all the traces are 0.2 mm.

I have changed this to 0.35 mm traces for all the oscilloscope lines.

The orientation of switch labels POWER and RESET are different from one another. The labels aren't even center aligned with the switches. Please focus on the aesthetics and fix those issues.

This is also fixed!

[Tejasgarg]

Regarding the layout, it mostly looks good except the ADC pin caps (C40/C41). They must be as close as possible to the actual pin on the MCU. The op-amp output resistors (R28/R29) should be kept close to the op-amp; the trace between R28/29 and C40/41 can be long-ish.

I have tried to reduce the distance between C40/41 to the MCU below 10 mm while also keeping the capacitor ground tied to the analog ground pour.

[Tejasgarg]

The op-amp rails should be decoupled with 100 nF close to the pins (3.3V and -2V). C29 is too far away; it should be within a few mm.

Now each power rail of the op amps has an individual 100nF decoupling capacitor.

The GDTs' ground should be connected directly to the BNC shells, not via signal ground vias.

Edit: Or even better, keep the vias but also add a wide path directly to the nearest BNC ground leg.

This is fixed, thanks for the suggestion :)

There is currently a single ground layer. We need to separate the two analog and digital ground planes. Please fix that too.

This is fixed as well!
Now there are two ground pours.
One under the oscilloscope front-end circuitry to reduce any type of transients from affecting it, and one under the rest of the board. They are connected to each other via two strips on the ends of the ground pours.

Also, Now both the input channels are symmetric and mirror images of each other to maximise the optimal use of space.

[CloudyPadmal]

There is no silkscreen around the components other than on the sides (have a look at the silkscreen render). Therefore a diagonally exiting ground via makes no sense. They also increase the length of the ground traces compared to a directly exiting trace.

Please remove all the diagonal ground traces and make them straight and place the vias closer to the pad (but not over the pad).

[bessman]

I have tried to reduce the distance between C40/41 to the MCU below 10 mm while also keeping the capacitor ground tied to the analog ground pour.

I really think they're still too far away. With ~10 mm of trace between the ADC pin and the cap, the inductance will cause large sampling kickback which will increase the settling time and potentially cause crosstalk.

If we can't get them closer than this without significant rearrangement, let's fab a prototype with this layout and see how it behaves. It might be OK for single MHz bandwidth.

[bessman]

Now each power rail of the op amps has an individual 100nF decoupling capacitor.

Looks good!

[CloudyPadmal]

I just noticed that the switch labels are facing downwards while all the other silkscreen labels are predominantly facing upwards. Rotate POWER and RESET switch labels by 180 degrees and make them center aligned with the mid point of switches.

There is also a discontinuity at the mid of CH2_IN line. Please fix that too.

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[Tejasgarg]

Please remove all the diagonal ground traces and make them straight and place the vias closer to the pad (but not over the pad).

Hi @CloudyPadmal!
I have changed all the ground traces to be straight now.

I really think they're still too far away. With ~10 mm of trace between the ADC pin and the cap, the inductance will cause large sampling kickback which will increase the settling time and potentially cause crosstalk.

Hey @bessman,
I have tried reducing this to be 3-5 mm now.
Let me know your thoughts on this, thanks!

I just noticed that the switch labels are facing downwards while all the other silkscreen labels are predominantly facing upwards. Rotate POWER and RESET switch labels by 180 degrees and make them center aligned with the mid point of switches.

Rotated and center aligned these.

Also noticed that it was actually showing up fine on my KiCad
But for some reason it was not showing up correctly in the output files.


Earlier, I was using Century Gothic for the font. I have switched this to the default KiCAD font to mitigate the alignment issue in the output files.

There is also a discontinuity at the mid of CH2_IN line. Please fix that too.

Fixed!