prio-bits feature for stm32 cortex-m0 chip

[versaloon]

I found in embassy-stm32 Cargo.toml file, the embassy-hal-internal dependency has a fixed feature prio-bits-4, but for CortexM0 from ST, the priority bits should be 2 which is 4 priority levels. Is it OK to use prio-bits-4 for CortexM0 chips?

[i509VCB]

That is probably an oversight in embassy-stm32. stm32-metapac has the info for how many prio bits there are, it would just mean enabling the right feature based on the selected chip.