-
Notifications
You must be signed in to change notification settings - Fork 5.2k
ARM64: Recognize more STP patterns #102126
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Conversation
|
Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch |
|
Have you looked into generalizing |
I have, but that was just a lot more work while here it's a few lines of code for -30kb diff, I guess this hack can be removed once |
|
Hmm, let me give it a quick try. I think the only hard part is extending the smarter interference check, but perhaps that's not necessary to get most cases. |
Sure, go ahead 🙂 |
|
It took a bit of finesse (and let's see what CI says), but #102133 has a prototype |
Hoping to see https://dev.azure.com/dnceng-public/public/_build/results?buildId=672905&view=ms.vss-build-web.run-extensions-tab diffs there as well 😉 |
When
LowerStoreIndirCoalescingfails to merge two stores it should at least make the stores STP-friendly (when it's legal). Example:Codegen diff (on arm64):
; Method Bench:Test(byref) (FullOpts) stp fp, lr, [sp, #-0x10]! mov fp, sp movi v16.4s, #0 - str q16, [x0] - movi v16.4s, #0 - str q16, [x0, #0x10] + movi v17.4s, #0 + stp q16, q17, [x0] ldp fp, lr, [sp], #0x10 ret lr -; Total bytes of code: 32 +; Total bytes of code: 28