DIVU Instruction not working correctly #28
Description
Page 44 of RISC-V ISA mandates "DIVU: Divides x[rs1] by x[rs2] rounding towards 0, treating the values as un-signed numbers and writes the quotient to x[rd]"
Our checker fails showing that the updates did not happen in cycle 38 to the register 2 in response to a prior divu instruction detected in cycle 37. x[26] is divided by x[19] and rd is 2. We expect x[2] to be 4 as x[26] is 8 and x[19] is 2, but it isn't.
