Improving Verilog support in FUGen and adding RFGen #279

Joonari · 2025-02-13T18:57:45Z

This improves the Verilog support in function unit generator (FUGen). Also adds a register file generator (RFGen). Similarly to FUGen, it takes RF information from an ADF and generates corresponding RTL in either Verilog or VHDL.

karihepola · 2025-02-14T06:47:49Z

openasip/src/applibs/HWGen/FUGen.cc

@@ -683,8 +684,10 @@ FUGen::buildOperations() {
        // Zero initialize this configuration to avoid simulation warnings
        if (isLSU_ && minLatency_ < 3) {


Are these redundant now? I suppose we must keep them if someone wants to force the '-' initialization. At least with Modelsim the 2 cycle LSU would have delta cycle warnings with don't care initializations, but should it be left for the user to decide?

Good point. My understanding is that some synthesis tools can better optimize the design when you use don't care initializations, but I don't know how large effect this has nowadays. We could just leave '0' as the default value due to simulation behaviour. Then if the user wants to try optimizations, they can enable the don't care initialization.

karihepola · 2025-02-14T07:06:09Z

openasip/hdb/generate_base32/vhdl/rotl.vhd

Are these used in the testsuite? Before, these would print warnings with ghdl every cycle.

karihepola · 2025-02-14T07:09:03Z

openasip/src/applibs/HWGen/FUGen.cc

@@ -827,11 +848,12 @@ FUGen::buildOperations() {
        } else {
            operationCp.addVariable(SignedVariable(v.name, w));
        }
-        // Zero initialize this configuration to avoid simulation warnings
        if (isLSU_ && minLatency_ < 3) {


karihepola · 2025-02-14T07:09:14Z

openasip/src/applibs/HWGen/FUGen.cc

@@ -841,12 +863,15 @@ FUGen::buildOperations() {
        // Zero initialize this configuration to avoid simulation warnings
        if (isLSU_ && minLatency_ < 3) {


pjaaskel

Mostly superficial comments from a quick glimpse. Good useful stuff. Quite many commits, next time perhaps check if you can squash some of the commits before pushing to make the history more easily readable/reviewable.

pjaaskel · 2025-03-14T12:25:56Z

openasip/src/applibs/HWGen/RFGen.cc

+}
+
+/**
+ *


Extra space before and after.

pjaaskel · 2025-03-14T12:26:13Z

openasip/src/applibs/HWGen/RFGen.hh

@@ -0,0 +1,86 @@
+/*
+ Copyright (C) 2024 Tampere University.


pjaaskel · 2025-03-14T12:26:59Z

openasip/src/applibs/HWGen/RFGen.cc

+/*
+ Copyright (C) 2024 Tampere University.
+
+ This library is free software; you can redistribute it and/or


We use LGPL v2.1 for the toolset files.

pjaaskel · 2025-03-14T12:28:02Z

openasip/src/applibs/ProGe/GeneratableRFNetlistBlock.hh

+
+namespace ProGe {
+
+    class GeneratableRFNetlistBlock : public NetlistBlock {


Do not indent because of the namespace.

pjaaskel · 2025-03-14T12:28:53Z

openasip/src/applibs/ProGe/ProGeUI.cc

@@ -622,22 +632,38 @@ ProGeUI::generateIDF(
        }
    }

-    // RFs.
+/*


Can you remove the commented out code or at least comment it out with #if 0?

pjaaskel · 2025-03-14T12:33:22Z

openasip/src/applibs/HWGen/HDLGenerator.hh

@@ -1503,6 +1503,9 @@ namespace HDLGenerator {
                       << ident << "use ieee.std_logic_1164.all;\n"
                       << ident << "use ieee.numeric_std.all;\n"
                       << ident << "use ieee.std_logic_misc.all;\n"
+                       << ident << "use STD.textio.all;\n"


ident? indent?

pjaaskel · 2025-03-14T12:33:56Z

openasip/src/applibs/HWGen/RFGen.cc

@@ -209,6 +254,77 @@ RFGen::createRFReadProcess() {
    behaviour_ << RawCodeLine(vhdlCode, verilogCode);
 }

+/*
+ * Create process to dump RF values into a file during simulation.
+ * Useful for debugging RISC-V machines, so create this


Add empty line after the brief comment.

pjaaskel · 2025-03-14T12:36:53Z

openasip/src/procgen/ProGe/ProGeCmdLineOptions.cc

+
+    BoolCmdLineOptionParser* dontCareInit = new BoolCmdLineOptionParser(
+        DONT_CARE_INIT,
+        "Initialize FUGen generated signals as don't care. E.g. some FPGA tool optimizations prefer these.");


pjaaskel · 2025-03-14T12:40:20Z

openasip/src/applibs/ProGe/TestBenchBlock.cc

@@ -102,15 +102,11 @@ TestBenchBlock::~TestBenchBlock() {
 void
 TestBenchBlock::write(const Path& targetBaseDir, HDL targetLang) const {
    // Check language compatibility //
-    std::cout << "--1" << std::endl;


Can you squash this with the commit that introduced the debug prints. Now there's 77 commits which is quite a lot? Fixup commits help to clean up the history.

pjaaskel · 2025-03-14T12:45:49Z

openasip/src/bintools/TestGenerator/generatetests

@@ -1,210 +0,0 @@
-#! /bin/bash


Can you just revert the commit where you added it or just squash this to it?

Can generate netlist block and RF ports now.

Signal formatting was missing a bracket when sign extending, and signal load_data_32b was not declared

Add --dont-care-init option to generateprocessor to initialize signals as ('-'). Don't care values cause issues in ASIC synthesis tools, so use '0' as the default init value.

…ature)

Change order of verilog include files containing parameter declarations, and add IMEMDATAWIDTH parameter to verilog package file

Module's 'd' port was initialized with zeroes. Verilog replication operator does not allow using a parameter of the same block to do this.

… VHDL

…cles in VHDL sim

… are also valid in verilog

Joonari · 2025-03-14T14:58:06Z

Fixed the style issues pointed out by @pjaaskel and squashed some commits to clean up the log.

pjaaskel · 2025-06-10T13:30:36Z

Is this ready?

pjaaskel requested review from karihepola and pjaaskel February 14, 2025 06:42

karihepola reviewed Feb 14, 2025

View reviewed changes

pjaaskel requested changes Mar 14, 2025

View reviewed changes

Joonari added 26 commits March 14, 2025 16:53

Add register file generator (RFGen)

bddc021

Can generate netlist block and RF ports now.

tcetest_bypass.sh: Add error message when itrace not correct

05b40ec

FUGen: Fix extra parenthesis and signal default value

916e020

Fix filename used in LSU RTL generation

78afcd0

FUGen: Fix verilog issues

d7ebb04

Signal formatting was missing a bracket when sign extending, and signal load_data_32b was not declared

Add verilog testbench template for the new TB generator

2b6c723

FUGen: Use don't care ('-') as signal init value only when specified

0baec96

Add --dont-care-init option to generateprocessor to initialize signals as ('-'). Don't care values cause issues in ASIC synthesis tools, so use '0' as the default init value.

WIP

f336828

Remove 'unique' from verilog case statements (it's a systemverilog fe…

94d907a

…ature)

Fix issues with verilog parameter definition

dda665b

Change order of verilog include files containing parameter declarations, and add IMEMDATAWIDTH parameter to verilog package file

Remove debug prints

9ba61ce

Fix SinglePortSSRAMBlock port width.

6bc6e84

Module's 'd' port was initialized with zeroes. Verilog replication operator does not allow using a parameter of the same block to do this.

Fix boolean parameter value in verilog HW generation

92028a1

Add clkgen.v

2e9fc43

Fix for loop in SRAM verilog model

61e8375

Fix parameters in SRAM verilog model

c6e6126

Fix verilog testbench template

f44a2a7

Add lsu_registers.v to HDB in generate.py

240886b

Add missing reset value for rdata_r in lsu_registers.vhdl

84c6c33

Add parameter default values

ad2038d

Fix port name in instantiated verilog modules

8f64814

Change verilog standard from 2001 to 2012 in iverilog compile script

619dea4

Remove debug prints

bd6ba62

Multiple fixes to verilog netlist writer

f4518cc

Fix issue with execution_count_reg

3901369

Compile files as SystemVerilog when using modelsim

ffe0ef8

Joonari and others added 24 commits March 14, 2025 16:53

Fix Verilog decoder lock signal generation

89c5910

Fix RFGen system test

deb33e6

Start adding FUGen Verilog tests. Bustrace mismatch.

0ea74bd

Fix conditional bash statement

9a2345b

Change RISC-V test RF dump expected output

5f6451f

Start cycle count from -1 in Verilog IC due to different behaviour to…

061b5df

… VHDL

Add mem init (in simulation) to synch_byte_mask_sram

cf85473

Verilog simulation: Add PERIOD to SIMTIME to match number of exec. cy…

43c12c7

…cles in VHDL sim

Fix defaults.v

759d819

Fix FUGen Verilog sign extension

effb7a2

Add FUGen Verilog tests. Failing tests commented out!

1cf698c

Add missing IDF file

dd1f810

Add parameter for max. num. processes when running system tests

6171517

Move missing RFGen files during install

c55ce34

Fix simulator warnings with rotation operations

6f9da4d

FUGen: Change ordering of suboperation result assignment so that they…

8a5ed50

… are also valid in verilog

FUGen: Fix width inspection for dag output

9befafe

More fixes for FUGen Verilog output

edaa9ac

Fix subop signal connections in FUGen

8761c83

Enable FUGen test that now passes

b24b76c

Add option to manually run CI workflows

31252ec

Remove now useless connection map

28e85f5

Add test generator (TeGe)

b85ff06

Remove file suffix from an operation name in generate_base32.hdb

c581faa

Joonari force-pushed the fugen-verilog-fixes branch from 965ca7a to c581faa Compare March 14, 2025 14:55

Joonari added 3 commits March 14, 2025 17:32

Update testrunner.py for python 3 instead of 2

8f5f591

Install iverilog in github workflow

bf22f27

Reduce mem sizes in ADFs to avoid excessive simulation memory usage

a77aaf6

		@@ -683,8 +684,10 @@ FUGen::buildOperations() {
		// Zero initialize this configuration to avoid simulation warnings
		if (isLSU_ && minLatency_ < 3) {

		@@ -841,12 +863,15 @@ FUGen::buildOperations() {
		// Zero initialize this configuration to avoid simulation warnings
		if (isLSU_ && minLatency_ < 3) {

+              }
+              /**
+               *


		namespace ProGe {

		class GeneratableRFNetlistBlock : public NetlistBlock {

@@ @@ -622,22 +632,38 @@ ProGeUI::generateIDF( @@
                       }
                   }
-                  // RFs.
+              /*

Improving Verilog support in FUGen and adding RFGen #279

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Joonari commented Feb 13, 2025

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Joonari commented Mar 14, 2025

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pjaaskel commented Jun 10, 2025

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karihepola Feb 14, 2025 •

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