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HierarchicalModuleName does not work with assert

Status: Open.

#5001 In chipsalliance/chisel;

· mtikekar opened on Aug 3, 2025

<code>stop(msg)</code> does not emit correct verilog

Status: Open.

#4996 In chipsalliance/chisel;

· mtikekar opened on Jul 30, 2025

Allow zero length VecInit()

Status: Open.

#4986 In chipsalliance/chisel;

· oharboe opened on Jul 22, 2025

Chisel asserts should give file and line number to Chisel as well as systemverilog

Status: Open.

#4984 In chipsalliance/chisel;

· oharboe opened on Jul 19, 2025

ImportedDefinitionExtModule does not include secret ports (bores)

Status: Open.

#4963 In chipsalliance/chisel;

· mwachs5 opened on Jun 29, 2025

Running Chisel in GitHub Action causes Firrtl permission error

Status: Open.

#4959 In chipsalliance/chisel;

· zhutmost opened on Jun 28, 2025

Use firrtl.bitcast operator for DataView/asTypeOf conversions

Status: Open.

#4958 In chipsalliance/chisel;

· sequencer opened on Jun 27, 2025

Confusing bundle connection behavior with SRAM API

Status: Open.

#4945 In chipsalliance/chisel;

· tymcauley opened on Jun 2, 2025

Naming Prefix Preserved Across Failing Tests

bug

Status: Open.

#4941 In chipsalliance/chisel;

· seldridge opened on May 27, 2025

[chiselsim] Questasim Support

feature request

Status: Open.

#4935 In chipsalliance/chisel;

· seldridge opened on May 23, 2025

Proposal: Standardized Property Metadata API for Chisel Based on IP-XACT

Status: Open.

#4932 In chipsalliance/chisel;

· sequencer opened on May 21, 2025

Warning occurs when the decoder fields chiselType is chiselEnum

Status: Open.

#4930 In chipsalliance/chisel;

· yizishun opened on May 20, 2025