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alaindargelasalaindargelas
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Merge pull request #4057 from alainmarcel/alainmarcel-patch-1
init port
2 parents 1e3ae51 + cd8111c commit fed3100

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10 files changed

+5679
-67
lines changed

10 files changed

+5679
-67
lines changed

‎src/DesignCompile/NetlistElaboration.cpp

Lines changed: 34 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -620,7 +620,16 @@ bool NetlistElaboration::elaborate_(ModuleInstance* instance, bool recurse) {
620620
assigns->push_back(assign);
621621
}
622622
}
623-
netlist->process_stmts(component->getProcesses());
623+
624+
UHDM::VectorOfprocess_stmt* processes = netlist->process_stmts();
625+
if (processes == nullptr) {
626+
netlist->process_stmts(component->getProcesses());
627+
} else {
628+
if (component->getProcesses())
629+
for (auto proc : *component->getProcesses()) {
630+
netlist->process_stmts()->push_back(proc);
631+
}
632+
}
624633
}
625634

626635
if (recurse) {
@@ -2408,7 +2417,10 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
24082417
parentNetlist->getSymbolTable().emplace(parentSymbol, obj);
24092418
if (netlist) netlist->getSymbolTable().emplace(signame, obj);
24102419

2411-
if (exp) {
2420+
if (exp && ((!signalIsPort) ||
2421+
(signalIsPort &&
2422+
(sig->getDirection() != VObjectType::paPortDir_Out)))) {
2423+
// Cont assign for input port
24122424
cont_assign* assign = s.MakeCont_assign();
24132425
assign->VpiNetDeclAssign(true);
24142426
fC->populateCoreMembers(id, id, assign);
@@ -2431,6 +2443,26 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
24312443
assigns = netlist->cont_assigns();
24322444
}
24332445
assigns->push_back(assign);
2446+
} else if (exp && signalIsPort &&
2447+
(sig->getDirection() == VObjectType::paPortDir_Out)) {
2448+
// Initial statement for output port
2449+
initial* init = s.MakeInitial();
2450+
UHDM::VectorOfprocess_stmt* processes = netlist->process_stmts();
2451+
if (processes == nullptr) {
2452+
netlist->process_stmts(s.MakeProcess_stmtVec());
2453+
processes = netlist->process_stmts();
2454+
}
2455+
netlist->process_stmts()->push_back(init);
2456+
UHDM::assignment* assign_stmt = s.MakeAssignment();
2457+
init->Stmt(assign_stmt);
2458+
UHDM::ref_obj* ref = s.MakeRef_obj();
2459+
ref->VpiName(sig->getName());
2460+
ref->VpiParent(assign_stmt);
2461+
fC->populateCoreMembers(sig->getNodeId(), sig->getNodeId(), ref);
2462+
assign_stmt->Lhs(ref);
2463+
fC->populateCoreMembers(id, id, assign_stmt);
2464+
assign_stmt->VpiParent(init);
2465+
assign_stmt->Rhs(exp);
24342466
}
24352467
} else {
24362468
// Vars

‎tests/Moves/Moves.log

Lines changed: 5184 additions & 0 deletions
Large diffs are not rendered by default.

‎tests/Moves/Moves.sl

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin

‎tests/Moves/dut.sv

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
2+
`define BOARD [8:0]
3+
4+
module FindMoveMask (
5+
Blk,
6+
Wht,
7+
Moves
8+
);
9+
10+
input `BOARD Blk;
11+
input `BOARD Wht;
12+
output `BOARD Moves;
13+
14+
// moves only allowed to empty squares
15+
wire `BOARD Emp = ~(Blk | Wht);
16+
17+
// Masks of moves considering the state in each of the 8 possible directions
18+
wire `BOARD Move_N;
19+
wire `BOARD Move_E;
20+
wire `BOARD Move_W;
21+
wire `BOARD Move_S;
22+
23+
// Combine all moves
24+
wire `BOARD Moves = Move_N | Move_E | Move_W | Move_S ;
25+
26+
// Create all moves
27+
assign Move_N [00] = 1'b0;
28+
assign Move_N [01] = 1'b0;
29+
assign Move_N [02] = 1'b0;
30+
assign Move_N [03] = 1'b0;
31+
assign Move_N [04] = 1'b0;
32+
assign Move_N [05] = 1'b0;
33+
assign Move_N [06] = Emp[06] && Wht[03] && Blk[00];
34+
assign Move_N [07] = Emp[07] && Wht[04] && Blk[01];
35+
assign Move_N [08] = Emp[08] && Wht[05] && Blk[02];
36+
37+
assign Move_E [00] = 1'b0;
38+
assign Move_E [01] = 1'b0;
39+
assign Move_E [02] = Emp[02] && Wht[01] && Blk[00];
40+
assign Move_E [03] = 1'b0;
41+
assign Move_E [04] = 1'b0;
42+
assign Move_E [05] = Emp[05] && Wht[04] && Blk[03];
43+
assign Move_E [06] = 1'b0;
44+
assign Move_E [07] = 1'b0;
45+
assign Move_E [08] = Emp[08] && Wht[07] && Blk[06];
46+
47+
assign Move_W [00] = Emp[00] && Wht[01] && Blk[02];
48+
assign Move_W [01] = 1'b0;
49+
assign Move_W [02] = 1'b0;
50+
assign Move_W [03] = Emp[03] && Wht[04] && Blk[05];
51+
assign Move_W [04] = 1'b0;
52+
assign Move_W [05] = 1'b0;
53+
assign Move_W [06] = Emp[06] && Wht[07] && Blk[08];
54+
assign Move_W [07] = 1'b0;
55+
assign Move_W [08] = 1'b0;
56+
57+
assign Move_S [00] = Emp[00] && Wht[03] && Blk[06];
58+
assign Move_S [01] = Emp[01] && Wht[04] && Blk[07];
59+
assign Move_S [02] = Emp[02] && Wht[05] && Blk[08];
60+
assign Move_S [03] = 1'b0;
61+
assign Move_S [04] = 1'b0;
62+
assign Move_S [05] = 1'b0;
63+
assign Move_S [06] = 1'b0;
64+
assign Move_S [07] = 1'b0;
65+
assign Move_S [08] = 1'b0;
66+
67+
endmodule

‎tests/PortInitVal/PortInitVal.log

Lines changed: 18 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -118,36 +118,38 @@ AST_DEBUG_END
118118
[INF:UH0706] Creating UHDM Model...
119119
=== UHDM Object Stats Begin (Non-Elaborated Model) ===
120120
always 1
121-
assignment 1
121+
assignment 2
122122
begin 1
123-
constant 9
124-
cont_assign 5
123+
constant 7
124+
cont_assign 3
125125
design 1
126126
event_control 1
127127
if_stmt 1
128-
logic_net 7
129-
logic_typespec 7
128+
initial 1
129+
logic_net 6
130+
logic_typespec 6
130131
module_inst 4
131132
port 2
132-
ref_obj 6
133-
ref_typespec 7
133+
ref_obj 7
134+
ref_typespec 6
134135
=== UHDM Object Stats End ===
135136
[INF:UH0707] Elaborating UHDM...
136137
=== UHDM Object Stats Begin (Elaborated Model) ===
137138
always 2
138-
assignment 2
139+
assignment 3
139140
begin 2
140-
constant 9
141-
cont_assign 8
141+
constant 7
142+
cont_assign 5
142143
design 1
143144
event_control 2
144145
if_stmt 2
145-
logic_net 7
146-
logic_typespec 7
146+
initial 1
147+
logic_net 6
148+
logic_typespec 6
147149
module_inst 4
148150
port 3
149-
ref_obj 11
150-
ref_typespec 8
151+
ref_obj 12
152+
ref_typespec 7
151153
=== UHDM Object Stats End ===
152154
[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/PortInitVal/slpp_all/surelog.uhdm ...
153155
[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/PortInitVal/slpp_all/checker/surelog.chk.html ...
@@ -407,21 +409,6 @@ design: (work@dut)
407409
|vpiLhs:
408410
\_logic_net: ([email protected]), line:2:14, endln:2:15
409411
|vpiContAssign:
410-
\_cont_assign: , line:1:13, endln:1:14
411-
|vpiParent:
412-
\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10
413-
|vpiNetDeclAssign:1
414-
|vpiRhs:
415-
\_constant: , line:3:24, endln:3:25
416-
|vpiParent:
417-
\_cont_assign: , line:1:13, endln:1:14
418-
|vpiDecompile:0
419-
|vpiSize:1
420-
|UINT:0
421-
|vpiConstType:9
422-
|vpiLhs:
423-
\_logic_net: ([email protected]), line:1:13, endln:1:14
424-
|vpiContAssign:
425412
\_cont_assign: , line:7:11, endln:7:16
426413
|vpiParent:
427414
\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10
@@ -445,6 +432,8 @@ design: (work@dut)
445432
\_logic_typespec: , line:3:16, endln:3:19
446433
\_logic_typespec: , line:2:9, endln:2:13
447434
\_logic_typespec: , line:3:16, endln:3:19
435+
|vpiParent:
436+
\_logic_net: ([email protected]), line:1:13, endln:1:14
448437
\_logic_typespec: , line:3:16, endln:3:19
449438
\_logic_typespec: , line:2:9, endln:2:13
450439
\_cont_assign: , line:2:14, endln:2:15
@@ -470,29 +459,6 @@ design: (work@dut)
470459
\_logic_typespec: , line:2:9, endln:2:13
471460
|vpiParent:
472461
\_ref_typespec: ([email protected])
473-
\_cont_assign: , line:1:13, endln:1:14
474-
|vpiParent:
475-
\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortInitVal/dut.sv, line:1:1, endln:9:10
476-
|vpiNetDeclAssign:1
477-
|vpiRhs:
478-
\_constant: , line:3:24, endln:3:25
479-
|vpiLhs:
480-
\_logic_net: ([email protected]), line:1:13, endln:1:14
481-
|vpiParent:
482-
\_cont_assign: , line:1:13, endln:1:14
483-
|vpiTypespec:
484-
\_ref_typespec: ([email protected])
485-
|vpiParent:
486-
\_logic_net: ([email protected]), line:1:13, endln:1:14
487-
|vpiFullName:[email protected]
488-
|vpiActual:
489-
\_logic_typespec: , line:3:16, endln:3:19
490-
|vpiName:b
491-
|vpiFullName:[email protected]
492-
|vpiNetType:48
493-
\_logic_typespec: , line:3:16, endln:3:19
494-
|vpiParent:
495-
\_ref_typespec: ([email protected])
496462
===================
497463
[ FATAL] : 0
498464
[ SYNTAX] : 0

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