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Merge pull request #4056 from alainmarcel/alainmarcel-patch-1
port init value as cont assign
2 parents 4d00e9a + 8362292 commit 1e3ae51

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10 files changed

+278
-83
lines changed

10 files changed

+278
-83
lines changed

‎src/DesignCompile/NetlistElaboration.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2408,7 +2408,7 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
24082408
parentNetlist->getSymbolTable().emplace(parentSymbol, obj);
24092409
if (netlist) netlist->getSymbolTable().emplace(signame, obj);
24102410

2411-
if (exp && (!signalIsPort)) {
2411+
if (exp) {
24122412
cont_assign* assign = s.MakeCont_assign();
24132413
assign->VpiNetDeclAssign(true);
24142414
fC->populateCoreMembers(id, id, assign);

‎tests/InstArray/InstArray.log

Lines changed: 86 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -86,31 +86,33 @@ AST_DEBUG_END
8686
[NTE:EL0511] Nb leaf instances: 2.
8787
[INF:UH0706] Creating UHDM Model...
8888
=== UHDM Object Stats Begin (Non-Elaborated Model) ===
89-
constant 21
89+
constant 23
90+
cont_assign 4
9091
design 1
91-
logic_net 5
92-
logic_typespec 8
92+
logic_net 7
93+
logic_typespec 10
9394
module_array 2
94-
module_inst 9
95+
module_inst 10
9596
module_typespec 2
9697
port 6
9798
range 8
9899
ref_obj 8
99-
ref_typespec 10
100+
ref_typespec 12
100101
=== UHDM Object Stats End ===
101102
[INF:UH0707] Elaborating UHDM...
102103
=== UHDM Object Stats Begin (Elaborated Model) ===
103-
constant 21
104+
constant 23
105+
cont_assign 8
104106
design 1
105-
logic_net 5
106-
logic_typespec 8
107+
logic_net 7
108+
logic_typespec 10
107109
module_array 2
108-
module_inst 9
110+
module_inst 10
109111
module_typespec 2
110112
port 11
111113
range 8
112114
ref_obj 17
113-
ref_typespec 15
115+
ref_typespec 17
114116
=== UHDM Object Stats End ===
115117
[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/InstArray/slpp_all/surelog.uhdm ...
116118
[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/InstArray/slpp_all/checker/surelog.chk.html ...
@@ -337,6 +339,21 @@ design: (work@top)
337339
\_logic_typespec: , line:7:7, endln:7:7
338340
|vpiInstance:
339341
\_module_inst: work@bus_conn ([email protected][0]), file:${SURELOG_DIR}/tests/InstArray/dut.sv, line:3:3, endln:3:37
342+
|vpiContAssign:
343+
\_cont_assign: , line:7:7, endln:7:13
344+
|vpiParent:
345+
\_module_inst: work@bus_conn ([email protected][0]), file:${SURELOG_DIR}/tests/InstArray/dut.sv, line:3:3, endln:3:37
346+
|vpiNetDeclAssign:1
347+
|vpiRhs:
348+
\_constant: , line:7:16, endln:7:20
349+
|vpiParent:
350+
\_cont_assign: , line:7:7, endln:7:13
351+
|vpiDecompile:1'b1
352+
|vpiSize:1
353+
|BIN:1
354+
|vpiConstType:3
355+
|vpiLhs:
356+
\_logic_net: ([email protected][0].datain), line:7:7, endln:7:13
340357
|vpiModule:
341358
\_module_inst: work@bus_conn ([email protected][1]), file:${SURELOG_DIR}/tests/InstArray/dut.sv, line:3:3, endln:3:37
342359
|vpiParent:
@@ -392,6 +409,21 @@ design: (work@top)
392409
\_logic_typespec: , line:7:7, endln:7:7
393410
|vpiInstance:
394411
\_module_inst: work@bus_conn ([email protected][1]), file:${SURELOG_DIR}/tests/InstArray/dut.sv, line:3:3, endln:3:37
412+
|vpiContAssign:
413+
\_cont_assign: , line:7:7, endln:7:13
414+
|vpiParent:
415+
\_module_inst: work@bus_conn ([email protected][1]), file:${SURELOG_DIR}/tests/InstArray/dut.sv, line:3:3, endln:3:37
416+
|vpiNetDeclAssign:1
417+
|vpiRhs:
418+
\_constant: , line:7:16, endln:7:20
419+
|vpiParent:
420+
\_cont_assign: , line:7:7, endln:7:13
421+
|vpiDecompile:1'b1
422+
|vpiSize:1
423+
|BIN:1
424+
|vpiConstType:3
425+
|vpiLhs:
426+
\_logic_net: ([email protected][1].datain), line:7:7, endln:7:13
395427
|vpiModuleArray:
396428
\_module_array: (work@bus_conn), line:3:13, endln:3:15
397429
|vpiParent:
@@ -478,12 +510,8 @@ design: (work@top)
478510
|vpiConstType:9
479511
\_logic_typespec: , line:7:7, endln:7:7
480512
\_logic_typespec: , line:7:7, endln:7:7
481-
|vpiParent:
482-
\_logic_net: ([email protected][0].datain), line:7:7, endln:7:13
483513
\_logic_typespec: , line:7:7, endln:7:7
484514
\_logic_typespec: , line:7:7, endln:7:7
485-
|vpiParent:
486-
\_logic_net: ([email protected][1].datain), line:7:7, endln:7:13
487515
\_module_typespec: (bus_conn), line:3:3, endln:3:11
488516
|vpiName:bus_conn
489517
\_logic_typespec: , line:7:7, endln:7:7
@@ -508,6 +536,50 @@ design: (work@top)
508536
|vpiSize:64
509537
|UINT:0
510538
|vpiConstType:9
539+
\_cont_assign: , line:7:7, endln:7:13
540+
|vpiParent:
541+
\_module_inst: work@bus_conn ([email protected][0]), file:${SURELOG_DIR}/tests/InstArray/dut.sv, line:3:3, endln:3:37
542+
|vpiNetDeclAssign:1
543+
|vpiRhs:
544+
\_constant: , line:7:16, endln:7:20
545+
|vpiLhs:
546+
\_logic_net: ([email protected][0].datain), line:7:7, endln:7:13
547+
|vpiParent:
548+
\_cont_assign: , line:7:7, endln:7:13
549+
|vpiTypespec:
550+
\_ref_typespec: ([email protected][0].datain)
551+
|vpiParent:
552+
\_logic_net: ([email protected][0].datain), line:7:7, endln:7:13
553+
|vpiFullName:[email protected][0].datain
554+
|vpiActual:
555+
\_logic_typespec: , line:7:7, endln:7:7
556+
|vpiName:datain
557+
|vpiFullName:[email protected][0].datain
558+
\_logic_typespec: , line:7:7, endln:7:7
559+
|vpiParent:
560+
\_ref_typespec: ([email protected][0].datain)
561+
\_cont_assign: , line:7:7, endln:7:13
562+
|vpiParent:
563+
\_module_inst: work@bus_conn ([email protected][1]), file:${SURELOG_DIR}/tests/InstArray/dut.sv, line:3:3, endln:3:37
564+
|vpiNetDeclAssign:1
565+
|vpiRhs:
566+
\_constant: , line:7:16, endln:7:20
567+
|vpiLhs:
568+
\_logic_net: ([email protected][1].datain), line:7:7, endln:7:13
569+
|vpiParent:
570+
\_cont_assign: , line:7:7, endln:7:13
571+
|vpiTypespec:
572+
\_ref_typespec: ([email protected][1].datain)
573+
|vpiParent:
574+
\_logic_net: ([email protected][1].datain), line:7:7, endln:7:13
575+
|vpiFullName:[email protected][1].datain
576+
|vpiActual:
577+
\_logic_typespec: , line:7:7, endln:7:7
578+
|vpiName:datain
579+
|vpiFullName:[email protected][1].datain
580+
\_logic_typespec: , line:7:7, endln:7:7
581+
|vpiParent:
582+
\_ref_typespec: ([email protected][1].datain)
511583
===================
512584
[ FATAL] : 0
513585
[ SYNTAX] : 0

‎tests/ModPortTest/ModPortTest.log

Lines changed: 36 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -300,26 +300,27 @@ PP TREE: (top_level_rule null_rule (source_text (description (module module)) (d
300300
[INF:UH0706] Creating UHDM Model...
301301
=== UHDM Object Stats Begin (Non-Elaborated Model) ===
302302
attribute 2
303-
constant 11
303+
constant 12
304+
cont_assign 2
304305
design 1
305306
enum_const 8
306307
enum_typespec 2
307308
enum_var 2
308309
interface_inst 4
309310
interface_typespec 9
310311
io_decl 7
311-
logic_net 13
312-
logic_typespec 8
312+
logic_net 14
313+
logic_typespec 9
313314
modport 7
314-
module_inst 7
315+
module_inst 8
315316
operation 4
316317
packed_array_typespec 1
317318
param_assign 1
318319
parameter 1
319320
port 9
320321
range 2
321322
ref_obj 11
322-
ref_typespec 19
323+
ref_typespec 20
323324
unsupported_typespec 3
324325
=== UHDM Object Stats End ===
325326
[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/ModPortTest/slpp_unit/surelog.uhdm ...
@@ -747,6 +748,33 @@ design: (work@dff0_test)
747748
|vpiFullName:work@dff0_test.n1
748749
|vpiActual:
749750
\_logic_typespec: , line:3:10, endln:3:10
751+
|vpiContAssign:
752+
\_cont_assign: , line:4:7, endln:4:9
753+
|vpiParent:
754+
\_module_inst: work@dff0_test (work@dff0_test), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:1:1, endln:5:10
755+
|vpiNetDeclAssign:1
756+
|vpiRhs:
757+
\_constant: , line:4:12, endln:4:17
758+
|vpiParent:
759+
\_cont_assign: , line:4:7, endln:4:9
760+
|vpiDecompile:32'd0
761+
|vpiSize:32
762+
|DEC:0
763+
|vpiConstType:1
764+
|vpiLhs:
765+
\_logic_net: (work@dff0_test.n1), line:4:7, endln:4:17
766+
|vpiParent:
767+
\_cont_assign: , line:4:7, endln:4:9
768+
|vpiTypespec:
769+
\_ref_typespec: (work@dff0_test.n1)
770+
|vpiParent:
771+
\_logic_net: (work@dff0_test.n1), line:4:7, endln:4:17
772+
|vpiFullName:work@dff0_test.n1
773+
|vpiActual:
774+
\_logic_typespec: , line:4:3, endln:4:6
775+
|vpiName:n1
776+
|vpiFullName:work@dff0_test.n1
777+
|vpiNetType:48
750778
|uhdmtopModules:
751779
\_module_inst: work@memory_ctrl1 (work@memory_ctrl1), file:${SURELOG_DIR}/tests/ModPortTest/top.v, line:36:1, endln:43:10
752780
|vpiParent:
@@ -976,8 +1004,6 @@ design: (work@dff0_test)
9761004
\_weaklyReferenced:
9771005
\_logic_typespec: , line:3:10, endln:3:10
9781006
\_logic_typespec: , line:4:3, endln:4:6
979-
|vpiParent:
980-
\_logic_net: (work@dff0_test.n1), line:4:7, endln:4:17
9811007
\_interface_typespec: (mem_if), line:36:22, endln:36:28
9821008
|vpiName:mem_if
9831009
\_logic_typespec: , line:29:25, endln:29:29
@@ -1013,6 +1039,9 @@ design: (work@dff0_test)
10131039
|vpiName:mem_if
10141040
\_unsupported_typespec: (DD), line:51:1, endln:51:3
10151041
|vpiName:DD
1042+
\_logic_typespec: , line:4:3, endln:4:6
1043+
|vpiParent:
1044+
\_ref_typespec: (work@dff0_test.n1)
10161045
===================
10171046
[ FATAL] : 0
10181047
[ SYNTAX] : 0

‎tests/PortDefaultValue/PortDefaultValue.log

Lines changed: 71 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -65,29 +65,31 @@ AST_DEBUG_END
6565
[NTE:EL0511] Nb leaf instances: 1.
6666
[INF:UH0706] Creating UHDM Model...
6767
=== UHDM Object Stats Begin (Non-Elaborated Model) ===
68-
constant 11
68+
constant 14
69+
cont_assign 2
6970
design 1
70-
logic_net 2
71-
logic_typespec 3
72-
module_inst 5
71+
logic_net 3
72+
logic_typespec 4
73+
module_inst 6
7374
port 2
74-
range 4
75+
range 5
7576
ref_module 1
7677
ref_obj 2
77-
ref_typespec 3
78+
ref_typespec 4
7879
=== UHDM Object Stats End ===
7980
[INF:UH0707] Elaborating UHDM...
8081
=== UHDM Object Stats Begin (Elaborated Model) ===
81-
constant 11
82+
constant 14
83+
cont_assign 3
8284
design 1
83-
logic_net 2
84-
logic_typespec 3
85-
module_inst 5
85+
logic_net 3
86+
logic_typespec 4
87+
module_inst 6
8688
port 3
87-
range 4
89+
range 5
8890
ref_module 1
8991
ref_obj 3
90-
ref_typespec 4
92+
ref_typespec 5
9193
=== UHDM Object Stats End ===
9294
[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/PortDefaultValue/slpp_all/surelog.uhdm ...
9395
[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/PortDefaultValue/slpp_all/checker/surelog.chk.html ...
@@ -211,6 +213,21 @@ design: (work@top)
211213
\_logic_typespec: , line:7:7, endln:7:12
212214
|vpiInstance:
213215
\_module_inst: work@bus_conn ([email protected]), file:${SURELOG_DIR}/tests/PortDefaultValue/dut.sv, line:3:1, endln:3:15
216+
|vpiContAssign:
217+
\_cont_assign: , line:7:13, endln:7:19
218+
|vpiParent:
219+
\_module_inst: work@bus_conn ([email protected]), file:${SURELOG_DIR}/tests/PortDefaultValue/dut.sv, line:3:1, endln:3:15
220+
|vpiNetDeclAssign:1
221+
|vpiRhs:
222+
\_constant: , line:7:22, endln:7:27
223+
|vpiParent:
224+
\_cont_assign: , line:7:13, endln:7:19
225+
|vpiDecompile:8'hFF
226+
|vpiSize:8
227+
|HEX:FF
228+
|vpiConstType:5
229+
|vpiLhs:
230+
\_logic_net: ([email protected]), line:7:13, endln:7:19
214231
\_weaklyReferenced:
215232
\_logic_typespec: , line:7:7, endln:7:12
216233
|vpiRange:
@@ -234,8 +251,6 @@ design: (work@top)
234251
|UINT:0
235252
|vpiConstType:9
236253
\_logic_typespec: , line:7:7, endln:7:12
237-
|vpiParent:
238-
\_logic_net: ([email protected]), line:7:13, endln:7:19
239254
|vpiRange:
240255
\_range: , line:7:7, endln:7:12
241256
|vpiParent:
@@ -277,6 +292,48 @@ design: (work@top)
277292
|vpiSize:64
278293
|UINT:0
279294
|vpiConstType:9
295+
\_cont_assign: , line:7:13, endln:7:19
296+
|vpiParent:
297+
\_module_inst: work@bus_conn ([email protected]), file:${SURELOG_DIR}/tests/PortDefaultValue/dut.sv, line:3:1, endln:3:15
298+
|vpiNetDeclAssign:1
299+
|vpiRhs:
300+
\_constant: , line:7:22, endln:7:27
301+
|vpiLhs:
302+
\_logic_net: ([email protected]), line:7:13, endln:7:19
303+
|vpiParent:
304+
\_cont_assign: , line:7:13, endln:7:19
305+
|vpiTypespec:
306+
\_ref_typespec: ([email protected])
307+
|vpiParent:
308+
\_logic_net: ([email protected]), line:7:13, endln:7:19
309+
|vpiFullName:[email protected]
310+
|vpiActual:
311+
\_logic_typespec: , line:7:7, endln:7:12
312+
|vpiName:datain
313+
|vpiFullName:[email protected]
314+
\_logic_typespec: , line:7:7, endln:7:12
315+
|vpiParent:
316+
\_ref_typespec: ([email protected])
317+
|vpiRange:
318+
\_range: , line:7:7, endln:7:12
319+
|vpiParent:
320+
\_logic_typespec: , line:7:7, endln:7:12
321+
|vpiLeftRange:
322+
\_constant: , line:7:8, endln:7:9
323+
|vpiParent:
324+
\_range: , line:7:7, endln:7:12
325+
|vpiDecompile:7
326+
|vpiSize:64
327+
|UINT:7
328+
|vpiConstType:9
329+
|vpiRightRange:
330+
\_constant: , line:7:10, endln:7:11
331+
|vpiParent:
332+
\_range: , line:7:7, endln:7:12
333+
|vpiDecompile:0
334+
|vpiSize:64
335+
|UINT:0
336+
|vpiConstType:9
280337
===================
281338
[ FATAL] : 0
282339
[ SYNTAX] : 0

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