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Add BSRAM operation check #328

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Merged
merged 1 commit into from
May 2, 2025
Merged

Add BSRAM operation check #328

merged 1 commit into from
May 2, 2025

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yrabbit
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@yrabbit yrabbit commented May 1, 2025

A femto-riscv-memtest example is added that contains riscv and firmware to test memory writes/reads.

Memory is checked after the end of the program and almost up to the maximum allowable address - whole chunks of 64 bytes are checked for simplicity of the program itself.

Implemented for Tangnano4k, Tangnano9k and Tangnano20k with 16K, 48K and 88K BSRAM check respectively.

Firmware source code in examples/riscv-firmware/memtest-src directory.

A femto-riscv-memtest example is added that contains riscv and firmware
to test memory writes/reads.

Memory is checked after the end of the program and almost up to the
maximum allowable address - whole chunks of 64 bytes are checked for
simplicity of the program itself.

Implemented for Tangnano4k, Tangnano9k and Tangnano20k with 16K, 48K and
88K BSRAM check respectively.

Firmware source code in examples/riscv-firmware/memtest-src directory.

Signed-off-by: YRabbit <[email protected]>
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yrabbit commented May 1, 2025

The point was to check bytes in total, not visually by pixels of VGA picture or indirectly by operability of Mandelbrot set calculation - there is no guarantee that all bytes work correctly.

In the terminal you can see the write/read result for each byte. Of course, it is not without disadvantages - the area of the program itself and up to 64 last bytes are not checked. Besides, only the primitives generated by the synthesis are checked :)

mem-start-20

mem-end-20

@yrabbit yrabbit merged commit 6a73072 into YosysHQ:master May 2, 2025
12 of 14 checks passed
@yrabbit yrabbit deleted the memtest branch May 2, 2025 10:12
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