Another issue with gowin_unpack.py

[pecostm32]

I found another issue where gowin_unpack.py fails with an error.
(<class 'KeyError'>, KeyError('RPLLB1'), <traceback object at 0x7ff14de41800>)

It is in the definition "def tile2verilog(dbrow, dbcol, bels, pips, clock_pips, mod, cst, db):" in section:

    elif typ.startswith("RPLL"):
        name = f"PLL_{idx}"
        pll = mod.primitives.setdefault(name, codegen.Primitive("rPLL", name))
        for paramval in flags:
            param, _, val = paramval.partition('=')
            pll.params[param] = val
        portmap = db.grid[dbrow][dbcol].bels[bel[:-1]].portmap
        for port, wname in portmap.items():
            pll.portmap[port] = f"R{row}C{col}_{wname}"

Debugging showed:
dbrow = 45
dbcol = 52
bel = 'RPLLB10'
bels = {'RPLLB10': {'CLKOUTPS="ENABLE"', 'PWDEN="ENABLE"', 'DUTYDA_SEL="1100"', 'DYN_SDIV_SEL=28', 'DEVICE="GW2A-18"', 'CLKOUTDIV3="ENABLE"', 'RSTEN="ENABLE"', 'PSDA_SEL="0111"'}}

It works fine when bel = "RPLLB1", but as soon at the second digit at the end comes in it fails. I changed "portmap = db.grid[dbrow][dbcol].bels[bel[:-1]].portmap" to "portmap = db.grid[dbrow][dbcol].bels[bel[:5]].portmap" and then it runs through without problems.

Attached is the bitstream I'm using. It is converted from a binary format back to the text format by me.
dso2d10_fpga.fs.zip

@pepijndevos I'm not sure if you get notified when new comment is added to a closed issue, but I added some to my other issue to point out my ideas on the documentation.

[pepijndevos]

Yes I saw your comment, thanks.

This change looks reasonable to me.