We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent bb2cdd6 commit 0610d6cCopy full SHA for 0610d6c
frontends/verific/verific.cc
@@ -3769,7 +3769,7 @@ struct VerificPass : public Pass {
3769
3770
// Run command to convert VHDL to Verilog
3771
std::string basename = FileSystem::Basename(filename);
3772
- std::string top = filename_str.substr(basename.find_last_of("/")+1, basename.find_last_of(".")-basename.find_last_of("/")-1);
+ std::string top = basename.substr(0, basename.find_last_of("."));
3773
std::string outfile = "preqorsor/data/" + top + ".v";
3774
std::string ghdl_cmd = ghdl_path + " --synth --no-formal -fsynopsys --out=verilog " + filename_str + " -e " + top + " > " + outfile;
3775
log("Running command: %s\n", ghdl_cmd.c_str());
0 commit comments