core: stdcm: cache engineering allowance sequences #12586
Merged
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We very often test several engineering allowances at the same place, with the same previous edges. This is done when we can get overtaken by more than one train at once at the same place, which is actually very common.
Caching the sequences avoids redundant computations. We still only evaluate what's necessary, and then use soft references to avoid ram issues.
Full bench data, +3% average peak ram, -25% processing time. Run with 6 GB limit.