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drivers: video: Himax HM01B0 camera sensor driver
Add Himax HM01B0 camera sensor driver. It depends on I2C and it is required to configure the camera. Signed-off-by: Antonino Scarpaci <[email protected]>
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‎drivers/video/CMakeLists.txt

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@@ -25,5 +25,6 @@ zephyr_library_sources_ifdef(CONFIG_VIDEO_EMUL_RX video_emul_rx.c)
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zephyr_library_sources_ifdef(CONFIG_VIDEO_IMX335 imx335.c)
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zephyr_library_sources_ifdef(CONFIG_VIDEO_ST_MIPID02 video_st_mipid02.c)
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zephyr_library_sources_ifdef(CONFIG_VIDEO_STM32_DCMIPP video_stm32_dcmipp.c)
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zephyr_library_sources_ifdef(CONFIG_VIDEO_HIMAX_HM01B0 hm01b0.c)
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zephyr_linker_sources(DATA_SECTIONS video.ld)

‎drivers/video/Kconfig

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@@ -84,6 +84,8 @@ source "drivers/video/Kconfig.ov9655"
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source "drivers/video/Kconfig.gc2145"
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source "drivers/video/Kconfig.hm01b0"
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source "drivers/video/Kconfig.mcux_sdma"
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source "drivers/video/Kconfig.emul_imager"

‎drivers/video/Kconfig.hm01b0

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# Copyright (c) 2025 The Zephyr Project Contributors
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# SPDX-License-Identifier: Apache-2.0
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config VIDEO_HIMAX_HM01B0
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bool "Real-time monochrome camera Himax HM01B0 sensor"
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depends on DT_HAS_HIMAX_HM01B0_ENABLED
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select I2C
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default y
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help
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Enable driver for monochrome camera Himax HM01B0 sensor.

‎drivers/video/hm01b0.c

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/*
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* Copyright The Zephyr Project Contributors
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT himax_hm01b0
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#include <zephyr/drivers/i2c.h>
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#include <zephyr/drivers/video-controls.h>
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#include <zephyr/drivers/video.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/sys/byteorder.h>
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#include <zephyr/sys/util.h>
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#include "video_device.h"
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#include "video_common.h"
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LOG_MODULE_REGISTER(hm01b0, CONFIG_VIDEO_LOG_LEVEL);
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#define MAX_FRAME_RATE 10
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#define MIN_FRAME_RATE 1
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#define HM01B0_ID 0x01B0
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#define HM01B0_REG8(addr) ((addr) | VIDEO_REG_ADDR16_DATA8)
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#define HM01B0_REG16(addr) ((addr) | VIDEO_REG_ADDR16_DATA16_BE)
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#define HM01B0_CCI_ID HM01B0_REG16(0x0000)
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#define HM01B0_CCI_STS HM01B0_REG8(0x0100)
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#define HM01B0_CCI_RESET HM01B0_REG8(0x0103)
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#define HM01B0_CCI_GRP_PARAM_HOLD HM01B0_REG8(0x0104)
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#define HM01B0_CCI_INTEGRATION_H HM01B0_REG16(0x0202)
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#define HM01B0_CCI_FRAME_LENGTH_LINES HM01B0_REG16(0x0340)
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#define HM01B0_CCI_LINE_LENGTH_PCLK HM01B0_REG16(0x0342)
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#define HM01B0_CCI_WIDTH HM01B0_REG8(0x0383)
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#define HM01B0_CCI_HEIGHT HM01B0_REG8(0x0387)
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#define HM01B0_CCI_BINNING_MODE HM01B0_REG8(0x0390)
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#define HM01B0_CCI_QVGA_WIN_EN HM01B0_REG8(0x3010)
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#define HM01B0_CCI_BIT_CONTROL HM01B0_REG8(0x3059)
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#define HM01B0_CCI_OSC_CLOCK_DIV HM01B0_REG8(0x3060)
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enum hm01b0_resolution {
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RESOLUTION_160x120,
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RESOLUTION_320x240,
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RESOLUTION_320x320,
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};
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struct video_reg hm01b0_160x120_regs[] = {
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{HM01B0_CCI_WIDTH, 0x3},
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{HM01B0_CCI_HEIGHT, 0x3},
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{HM01B0_CCI_BINNING_MODE, 0x3},
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{HM01B0_CCI_QVGA_WIN_EN, 0x1},
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{HM01B0_CCI_FRAME_LENGTH_LINES, 0x80},
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{HM01B0_CCI_LINE_LENGTH_PCLK, 0xD7},
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};
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struct video_reg hm01b0_320x240_regs[] = {
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{HM01B0_CCI_WIDTH, 0x1},
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{HM01B0_CCI_HEIGHT, 0x1},
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{HM01B0_CCI_BINNING_MODE, 0x0},
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{HM01B0_CCI_QVGA_WIN_EN, 0x1},
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{HM01B0_CCI_FRAME_LENGTH_LINES, 0x104},
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{HM01B0_CCI_LINE_LENGTH_PCLK, 0x178},
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};
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struct video_reg hm01b0_320x320_regs[] = {
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{HM01B0_CCI_WIDTH, 0x1},
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{HM01B0_CCI_HEIGHT, 0x1},
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{HM01B0_CCI_BINNING_MODE, 0x0},
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{HM01B0_CCI_QVGA_WIN_EN, 0x0},
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{HM01B0_CCI_FRAME_LENGTH_LINES, 0x158},
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{HM01B0_CCI_LINE_LENGTH_PCLK, 0x178},
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};
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struct video_reg *hm01b0_init_regs[] = {
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[RESOLUTION_160x120] = hm01b0_160x120_regs,
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[RESOLUTION_320x240] = hm01b0_320x240_regs,
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[RESOLUTION_320x320] = hm01b0_320x320_regs,
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};
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struct hm01b0_data {
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struct video_format fmt;
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uint8_t ctrl_val;
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};
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struct hm01b0_config {
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const struct i2c_dt_spec i2c;
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const uint8_t data_bits;
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};
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#define HM01B0_VIDEO_FORMAT_CAP(width, height, format) \
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{ \
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.pixelformat = (format), \
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.width_min = (width), \
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.width_max = (width), \
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.height_min = (height), \
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.height_max = (height), \
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.width_step = 0, \
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.height_step = 0, \
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}
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static const struct video_format_cap hm01b0_fmts[] = {
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HM01B0_VIDEO_FORMAT_CAP(160, 120, VIDEO_PIX_FMT_GREY),
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HM01B0_VIDEO_FORMAT_CAP(320, 240, VIDEO_PIX_FMT_GREY),
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HM01B0_VIDEO_FORMAT_CAP(320, 320, VIDEO_PIX_FMT_GREY),
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{0},
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};
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static int hm01b0_apply_configuration(const struct device *dev, enum hm01b0_resolution resolution)
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{
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struct hm01b0_data *data = dev->data;
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const struct hm01b0_config *config = dev->config;
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int ret;
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/* Number of registers is the same for all configuration */
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ret = video_write_cci_multiregs(&config->i2c, hm01b0_init_regs[resolution],
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ARRAY_SIZE(hm01b0_160x120_regs));
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if (ret != 0) {
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LOG_ERR("Failed to write config list registers (%d)", ret);
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return ret;
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}
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/* REG_BIT_CONTROL */
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ret = video_write_cci_reg(&config->i2c, HM01B0_CCI_BIT_CONTROL, data->ctrl_val);
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if (ret != 0) {
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LOG_ERR("Failed to write BIT_CONTROL reg (%d)", ret);
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return ret;
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}
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/* OSC_CLK_DIV */
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ret = video_write_cci_reg(&config->i2c, HM01B0_CCI_OSC_CLOCK_DIV, 0x08);
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if (ret != 0) {
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LOG_ERR("Failed to write OSC_CLK_DIV reg (%d)", ret);
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return ret;
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}
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/* INTEGRATION_H */
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ret = video_write_cci_reg(&config->i2c, HM01B0_CCI_INTEGRATION_H,
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hm01b0_init_regs[resolution][5].data / 2);
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if (ret != 0) {
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LOG_ERR("Failed to write INTEGRATION_H reg (%d)", ret);
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return ret;
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}
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/* GRP_PARAM_HOLD */
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ret = video_write_cci_reg(&config->i2c, HM01B0_CCI_GRP_PARAM_HOLD, 0x01);
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if (ret != 0) {
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LOG_ERR("Failed to write GRP_PARAM_HOLD reg (%d)", ret);
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return ret;
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}
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return ret;
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}
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static int hm01b0_get_caps(const struct device *dev, struct video_caps *caps)
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{
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caps->min_vbuf_count = 0;
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caps->min_line_count = LINE_COUNT_HEIGHT;
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caps->max_line_count = LINE_COUNT_HEIGHT;
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caps->format_caps = hm01b0_fmts;
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return 0;
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}
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static int hm01b0_set_fmt(const struct device *dev, struct video_format *fmt)
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{
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struct hm01b0_data *data = dev->data;
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size_t idx;
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int ret;
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LOG_DBG("HM01B0 set_fmt: %d x %d, fmt: %s", fmt->width, fmt->height,
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VIDEO_FOURCC_TO_STR(fmt->pixelformat));
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ret = video_format_caps_index(hm01b0_fmts, fmt, &idx);
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if (ret != 0) {
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LOG_ERR("Image resolution not supported\n");
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return ret;
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}
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if (!memcmp(&data->fmt, fmt, sizeof(data->fmt))) {
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return 0;
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}
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/* Check if camera is capable of handling given format */
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ret = hm01b0_apply_configuration(dev, (enum hm01b0_resolution)idx);
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if (ret != 0) {
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/* Camera is not capable of handling given format */
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LOG_ERR("Image resolution not supported");
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return ret;
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}
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data->fmt = *fmt;
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return ret;
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}
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static int hm01b0_get_fmt(const struct device *dev, struct video_format *fmt)
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{
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struct hm01b0_data *data = dev->data;
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*fmt = data->fmt;
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LOG_DBG("HM01B0 get_fmt: %d x %d, fmt: %s", fmt->width, fmt->height,
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VIDEO_FOURCC_TO_STR(fmt->pixelformat));
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return 0;
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}
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static int hm01b0_set_stream(const struct device *dev, bool enable, enum video_buf_type type)
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{
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const struct hm01b0_config *config = dev->config;
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/* SET MODE_SELECT */
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return video_write_cci_reg(&config->i2c, HM01B0_CCI_STS, enable ? 1 : 0);
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}
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static int hm01b0_soft_reset(const struct device *dev)
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{
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const struct hm01b0_config *config = dev->config;
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uint32_t val = 0xff;
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int ret;
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ret = video_write_cci_reg(&config->i2c, HM01B0_CCI_RESET, 0x01);
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if (ret != 0) {
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LOG_ERR("Error writing HM01B0_CCI_RESET (%d)", ret);
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return ret;
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}
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for (int retries = 0; retries < 10; retries++) {
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ret = video_read_cci_reg(&config->i2c, HM01B0_CCI_STS, &val);
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if (ret != 0 || val == 0x0) {
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break;
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}
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k_msleep(100);
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}
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if (ret != 0) {
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LOG_ERR("Soft reset error (%d)", ret);
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}
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return ret;
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}
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static DEVICE_API(video, hm01b0_driver_api) = {
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.set_format = hm01b0_set_fmt,
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.get_format = hm01b0_get_fmt,
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.set_stream = hm01b0_set_stream,
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.get_caps = hm01b0_get_caps,
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};
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static bool hm01b0_check_connection(const struct device *dev)
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{
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const struct hm01b0_config *config = dev->config;
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uint32_t model_id;
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int ret;
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ret = video_read_cci_reg(&config->i2c, HM01B0_CCI_ID, &model_id);
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if (ret != 0) {
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LOG_ERR("Error reading id reg (%d)", ret);
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return false;
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}
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return (model_id == HM01B0_ID);
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}
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static int hm01b0_init(const struct device *dev)
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{
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struct hm01b0_data *data = dev->data;
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const struct hm01b0_config *config = dev->config;
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int ret;
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if (config->data_bits == 8) {
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data->ctrl_val = 0x02;
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} else if (config->data_bits == 4) {
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data->ctrl_val = 0x42;
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} else if (config->data_bits == 1) {
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data->ctrl_val = 0x22;
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} else {
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LOG_ERR("Invalid data bits!");
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return -ENODEV;
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}
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if (!hm01b0_check_connection(dev)) {
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LOG_ERR("%s is not ready", dev->name);
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return -ENODEV;
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}
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ret = hm01b0_soft_reset(dev);
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if (ret != 0) {
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LOG_ERR("error sof reset (%d)", ret);
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return ret;
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}
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struct video_format fmt = {
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.pixelformat = VIDEO_PIX_FMT_GREY,
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.width = 160,
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.height = 120,
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.type = VIDEO_BUF_TYPE_OUTPUT,
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.pitch = 160 * video_bits_per_pixel(VIDEO_PIX_FMT_GREY) / BITS_PER_BYTE,
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};
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ret = hm01b0_set_fmt(dev, &fmt);
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if (ret != 0) {
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LOG_ERR("Error setting video format (%d)", ret);
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return ret;
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}
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return 0;
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}
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#define HM01B0_INIT(inst) \
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const struct hm01b0_config hm01b0_config_##inst = { \
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.i2c = I2C_DT_SPEC_INST_GET(inst), \
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.data_bits = DT_INST_PROP(inst, data_bits), \
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}; \
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struct hm01b0_data hm01b0_data_##inst; \
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DEVICE_DT_INST_DEFINE(inst, &hm01b0_init, NULL, &hm01b0_data_##inst, \
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&hm01b0_config_##inst, POST_KERNEL, CONFIG_VIDEO_INIT_PRIORITY, \
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&hm01b0_driver_api); \
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VIDEO_DEVICE_DEFINE(hm01b0_##inst, DEVICE_DT_INST_GET(inst), NULL);
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DT_INST_FOREACH_STATUS_OKAY(HM01B0_INIT)

‎dts/bindings/video/himax,hm01b0.yaml

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#
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# Copyright The Zephyr Project Contributors
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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description: |
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Himax HM01B0 video sensor.
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Example of node configuration:
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&i2c0 {
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status = "okay";
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hm01b0: hm01b0@24 {
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compatible = "himax,hm01b0";
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reg = <0x24>;
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status = "okay";
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data-bits = <0x4>;
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port {
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hm01b0_ep_out: endpoint {
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remote-endpoint-label = "video_pio_dma_ep_in";
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};
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};
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};
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};
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compatible: "himax,hm01b0"
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properties:
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data-bits:
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type: int
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default: 0x1
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description: Camera input data width. 1/4/8 bits
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enum: [1, 4, 8]
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include: i2c-device.yaml
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child-binding:
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child-binding:
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include: video-interfaces.yaml

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