Skip to content

Commit 63631f7

Browse files
stuijstuij
committed
[AArch64][SVE] Use FeatureUseFixedOverScalableIfEqualCost for A320
Downstream issue: arm#482 With this new A320 in-order core, we follow adding the FeatureUseFixedOverScalableIfEqualCost feature to A510 and A520 (#132246), which reaps the same code generation benefits of preferring fixed over scalable when the cost is equal. So when we have: ``` void foo(float* a, float* b, float* dst, unsigned n) { for (unsigned i = 0; i < n; ++i) dst[i] = a[i] + b[i]; } ``` When compiling without the feature enabled, we get: ``` ... ld1b { z0.b }, p0/z, [x0, x10] ld1b { z2.b }, p0/z, [x1, x10] add x12, x0, x10 ldr z1, [x12, arm#1, mul vl] add x12, x1, x10 ldr z3, [x12, arm#1, mul vl] fadd z0.s, z2.s, z0.s add x12, x2, x10 fadd z1.s, z3.s, z1.s dech x11 st1b { z0.b }, p0, [x2, x10] incb x10, all, mul arm#2 str z1, [x12, arm#1, mul vl] ... ``` When compiling with, we get: ``` ... ldp q0, q1, [x12, #-16] ldp q2, q3, [x11, #-16] subs x13, x13, arm#8 fadd v0.4s, v2.4s, v0.4s fadd v1.4s, v3.4s, v1.4s add x11, x11, arm#32 add x12, x12, arm#32 stp q0, q1, [x10, #-16] add x10, x10, arm#32 ... ``` This patch also moves FeatureUseFixedOverScalableIfEqualCost for A510 and A520 from the CPU features to the tune features.
1 parent a1cc67e commit 63631f7

File tree

2 files changed

+95
-5
lines changed

2 files changed

+95
-5
lines changed

‎llvm/lib/Target/AArch64/AArch64Processors.td

Lines changed: 19 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,11 @@ def TuneA320 : SubtargetFeature<"a320", "ARMProcFamily", "CortexA320",
2121
"Cortex-A320 ARM processors", [
2222
FeatureFuseAES,
2323
FeatureFuseAdrpAdd,
24-
FeaturePostRAScheduler]>;
24+
FeaturePostRAScheduler,
25+
// Downstream issue: #482 (Use
26+
// FeatureUseFixedOverScalableIfEqualCost
27+
// for A320)
28+
FeatureUseFixedOverScalableIfEqualCost]>;
2529

2630
def TuneA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
2731
"Cortex-A53 ARM processors", [
@@ -41,14 +45,22 @@ def TuneA510 : SubtargetFeature<"a510", "ARMProcFamily", "CortexA510",
4145
"Cortex-A510 ARM processors", [
4246
FeatureFuseAES,
4347
FeatureFuseAdrpAdd,
44-
FeaturePostRAScheduler
48+
FeaturePostRAScheduler,
49+
// Downstream issue: #482 (Use
50+
// FeatureUseFixedOverScalableIfEqualCost
51+
// for A320)
52+
FeatureUseFixedOverScalableIfEqualCost
4553
]>;
4654

4755
def TuneA520 : SubtargetFeature<"a520", "ARMProcFamily", "CortexA520",
4856
"Cortex-A520 ARM processors", [
4957
FeatureFuseAES,
5058
FeatureFuseAdrpAdd,
51-
FeaturePostRAScheduler]>;
59+
FeaturePostRAScheduler,
60+
// Downstream issue: #482 (Use
61+
// FeatureUseFixedOverScalableIfEqualCost
62+
// for A320)
63+
FeatureUseFixedOverScalableIfEqualCost]>;
5264

5365
def TuneA520AE : SubtargetFeature<"a520ae", "ARMProcFamily", "CortexA520",
5466
"Cortex-A520AE ARM processors", [
@@ -750,7 +762,8 @@ def ProcessorFeatures {
750762
FeatureSB, FeaturePAuth, FeatureSSBS, FeatureSVE, FeatureSVE2,
751763
FeatureComplxNum, FeatureCRC, FeatureDotProd,
752764
FeatureFPARMv8,FeatureFullFP16, FeatureJS, FeatureLSE,
753-
FeatureUseFixedOverScalableIfEqualCost,
765+
// Downstream issue: #482 (Use
766+
// FeatureUseFixedOverScalableIfEqualCost for A320)
754767
FeatureRAS, FeatureRCPC, FeatureRDM, FeatureFPAC];
755768
list<SubtargetFeature> A520 = [HasV9_2aOps, FeaturePerfMon, FeatureAM,
756769
FeatureMTE, FeatureETE, FeatureSVEBitPerm,
@@ -760,7 +773,8 @@ def ProcessorFeatures {
760773
FeatureSVE, FeatureSVE2, FeatureBF16, FeatureComplxNum, FeatureCRC,
761774
FeatureFPARMv8, FeatureFullFP16, FeatureMatMulInt8, FeatureJS,
762775
FeatureNEON, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM,
763-
FeatureUseFixedOverScalableIfEqualCost,
776+
// Downstream issue: #482 (Use
777+
// FeatureUseFixedOverScalableIfEqualCost for A320)
764778
FeatureDotProd, FeatureFPAC];
765779
list<SubtargetFeature> A520AE = [HasV9_2aOps, FeaturePerfMon, FeatureAM,
766780
FeatureMTE, FeatureETE, FeatureSVEBitPerm,

‎llvm/test/Transforms/LoopVectorize/AArch64/sve-fixed-width-inorder-core.ll

Lines changed: 76 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
22
; RUN: opt < %s -mtriple=aarch64-none-elf -mcpu=cortex-a510 -mattr=+sve -passes=loop-vectorize -S | FileCheck %s --check-prefix=CHECK-CA510
33
; RUN: opt < %s -mtriple=aarch64-none-elf -mcpu=cortex-a520 -mattr=+sve -passes=loop-vectorize -S | FileCheck %s --check-prefix=CHECK-CA520
4+
; NOTE: Downstream issue: #482 (Use FeatureUseFixedOverScalableIfEqualCost for A320)
5+
; RUN: opt < %s -mtriple=aarch64-none-elf -mcpu=cortex-a320 -mattr=+sve -passes=loop-vectorize -S | FileCheck %s --check-prefix=CHECK-CA320
46

57
define void @sve_add(ptr %dst, ptr %a, ptr %b, i64 %n) {
68
; CHECK-CA510-LABEL: define void @sve_add(
@@ -137,6 +139,74 @@ define void @sve_add(ptr %dst, ptr %a, ptr %b, i64 %n) {
137139
; CHECK-CA520: [[FOR_COND_CLEANUP]]:
138140
; CHECK-CA520-NEXT: ret void
139141
;
142+
; NOTE: Downstream issue: #482 (Use FeatureUseFixedOverScalableIfEqualCost for A320)
143+
; CHECK-CA320-LABEL: define void @sve_add(
144+
; CHECK-CA320-SAME: ptr [[DST:%.*]], ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
145+
; CHECK-CA320-NEXT: [[ENTRY:.*:]]
146+
; CHECK-CA320-NEXT: [[B3:%.*]] = ptrtoint ptr [[B]] to i64
147+
; CHECK-CA320-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i64
148+
; CHECK-CA320-NEXT: [[DST1:%.*]] = ptrtoint ptr [[DST]] to i64
149+
; CHECK-CA320-NEXT: [[CMP9_NOT:%.*]] = icmp eq i64 [[N]], 0
150+
; CHECK-CA320-NEXT: br i1 [[CMP9_NOT]], label %[[FOR_COND_CLEANUP:.*]], label %[[FOR_BODY_PREHEADER:.*]]
151+
; CHECK-CA320: [[FOR_BODY_PREHEADER]]:
152+
; CHECK-CA320-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8
153+
; CHECK-CA320-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
154+
; CHECK-CA320: [[VECTOR_MEMCHECK]]:
155+
; CHECK-CA320-NEXT: [[TMP0:%.*]] = sub i64 [[DST1]], [[A2]]
156+
; CHECK-CA320-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], 32
157+
; CHECK-CA320-NEXT: [[TMP1:%.*]] = sub i64 [[DST1]], [[B3]]
158+
; CHECK-CA320-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP1]], 32
159+
; CHECK-CA320-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
160+
; CHECK-CA320-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
161+
; CHECK-CA320: [[VECTOR_PH]]:
162+
; CHECK-CA320-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 8
163+
; CHECK-CA320-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
164+
; CHECK-CA320-NEXT: br label %[[VECTOR_BODY:.*]]
165+
; CHECK-CA320: [[VECTOR_BODY]]:
166+
; CHECK-CA320-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
167+
; CHECK-CA320-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw float, ptr [[A]], i64 [[INDEX]]
168+
; CHECK-CA320-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw float, ptr [[TMP2]], i32 0
169+
; CHECK-CA320-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw float, ptr [[TMP2]], i32 4
170+
; CHECK-CA320-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP13]], align 4
171+
; CHECK-CA320-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x float>, ptr [[TMP3]], align 4
172+
; CHECK-CA320-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw float, ptr [[B]], i64 [[INDEX]]
173+
; CHECK-CA320-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw float, ptr [[TMP4]], i32 0
174+
; CHECK-CA320-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw float, ptr [[TMP4]], i32 4
175+
; CHECK-CA320-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x float>, ptr [[TMP14]], align 4
176+
; CHECK-CA320-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x float>, ptr [[TMP5]], align 4
177+
; CHECK-CA320-NEXT: [[TMP6:%.*]] = fadd fast <4 x float> [[WIDE_LOAD6]], [[WIDE_LOAD]]
178+
; CHECK-CA320-NEXT: [[TMP7:%.*]] = fadd fast <4 x float> [[WIDE_LOAD7]], [[WIDE_LOAD5]]
179+
; CHECK-CA320-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw float, ptr [[DST]], i64 [[INDEX]]
180+
; CHECK-CA320-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw float, ptr [[TMP8]], i32 0
181+
; CHECK-CA320-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw float, ptr [[TMP8]], i32 4
182+
; CHECK-CA320-NEXT: store <4 x float> [[TMP6]], ptr [[TMP15]], align 4
183+
; CHECK-CA320-NEXT: store <4 x float> [[TMP7]], ptr [[TMP9]], align 4
184+
; CHECK-CA320-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
185+
; CHECK-CA320-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
186+
; CHECK-CA320-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
187+
; CHECK-CA320: [[MIDDLE_BLOCK]]:
188+
; CHECK-CA320-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
189+
; CHECK-CA320-NEXT: br i1 [[CMP_N]], label %[[FOR_COND_CLEANUP_LOOPEXIT:.*]], label %[[SCALAR_PH]]
190+
; CHECK-CA320: [[SCALAR_PH]]:
191+
; CHECK-CA320-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_BODY_PREHEADER]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
192+
; CHECK-CA320-NEXT: br label %[[FOR_BODY:.*]]
193+
; CHECK-CA320: [[FOR_BODY]]:
194+
; CHECK-CA320-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
195+
; CHECK-CA320-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[A]], i64 [[INDVARS_IV]]
196+
; CHECK-CA320-NEXT: [[TMP11:%.*]] = load float, ptr [[ARRAYIDX]], align 4
197+
; CHECK-CA320-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[B]], i64 [[INDVARS_IV]]
198+
; CHECK-CA320-NEXT: [[TMP12:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
199+
; CHECK-CA320-NEXT: [[ADD:%.*]] = fadd fast float [[TMP12]], [[TMP11]]
200+
; CHECK-CA320-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[DST]], i64 [[INDVARS_IV]]
201+
; CHECK-CA320-NEXT: store float [[ADD]], ptr [[ARRAYIDX4]], align 4
202+
; CHECK-CA320-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
203+
; CHECK-CA320-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[N]]
204+
; CHECK-CA320-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_COND_CLEANUP_LOOPEXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
205+
; CHECK-CA320: [[FOR_COND_CLEANUP_LOOPEXIT]]:
206+
; CHECK-CA320-NEXT: br label %[[FOR_COND_CLEANUP]]
207+
; CHECK-CA320: [[FOR_COND_CLEANUP]]:
208+
; CHECK-CA320-NEXT: ret void
209+
;
140210
entry:
141211
%cmp9.not = icmp eq i64 %n, 0
142212
br i1 %cmp9.not, label %for.cond.cleanup, label %for.body
@@ -166,3 +236,9 @@ for.cond.cleanup: ; preds = %for.cond.cleanup.lo
166236
; CHECK-CA520: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
167237
; CHECK-CA520: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
168238
;.
239+
; NOTE: Downstream issue: #482 (Use FeatureUseFixedOverScalableIfEqualCost for A320).
240+
; CHECK-CA320: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
241+
; CHECK-CA320: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
242+
; CHECK-CA320: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
243+
; CHECK-CA320: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
244+
;.

0 commit comments

Comments
 (0)