11-- ================================================================================ --
22-- NEORV32 SoC - Custom Functions Subsystem (CFS) --
33-- -------------------------------------------------------------------------------- --
4- -- Intended for tightly-coupled, application-specific custom co-processors. This --
5- -- module provides up to 64x 32-bit memory-mapped interface registers, one CPU --
6- -- interrupt request signal and custom IO conduits for processor-external or chip- --
7- -- external interface. --
8- -- -------------------------------------------------------------------------------- --
94-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
105-- Copyright (c) NEORV32 contributors. --
116-- Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. --
@@ -23,8 +18,8 @@ use neorv32.neorv32_package.all;
2318entity neorv32_cfs is
2419 generic (
2520 CFS_CONFIG : std_ulogic_vector (31 downto 0 ); -- custom CFS configuration generic
26- CFS_IN_SIZE : natural ; -- size of CFS input conduit in bits
27- CFS_OUT_SIZE : natural -- size of CFS output conduit in bits
21+ CFS_IN_SIZE : natural range 0 to 4096 ; -- size of CFS input conduit in bits
22+ CFS_OUT_SIZE : natural range 0 to 4096 -- size of CFS output conduit in bits
2823 );
2924 port (
3025 clk_i : in std_ulogic ; -- global clock line
@@ -34,8 +29,8 @@ entity neorv32_cfs is
3429 clkgen_en_o : out std_ulogic ; -- enable clock generator
3530 clkgen_i : in std_ulogic_vector (7 downto 0 ); -- "clock" inputs
3631 irq_o : out std_ulogic ; -- interrupt request
37- cfs_in_i : in std_ulogic_vector (CFS_IN_SIZE- 1 downto 0 ); -- custom inputs
38- cfs_out_o : out std_ulogic_vector (CFS_OUT_SIZE- 1 downto 0 ) -- custom outputs
32+ cfs_in_i : in std_ulogic_vector (CFS_IN_SIZE- 1 downto 0 ); -- custom inputs conduit
33+ cfs_out_o : out std_ulogic_vector (CFS_OUT_SIZE- 1 downto 0 ) -- custom outputs conduit
3934 );
4035end neorv32_cfs ;
4136
7166 -- -------------------------------------------------------------------------------------------
7267 -- The CFS can be reset using the global rstn_i signal. This signal should be used as asynchronous reset and is active-low.
7368 -- Note that rstn_i can be asserted by a processor-external reset, the on-chip debugger and also by the watchdog.
74- --
75- -- Most default peripheral devices of the NEORV32 do NOT use a dedicated hardware reset at all. Instead, these units are
76- -- reset by writing ZERO to a specific "control register" located right at the beginning of the device's address space
77- -- (so this register is cleared at first). The crt0 start-up code writes ZERO to every single address in the processor's
78- -- IO space - including the CFS. Make sure that this initial clearing does not cause any unintended CFS actions.
7969
8070
8171 -- Clock System ---------------------------------------------------------------------------
8474 -- Actually, these signals should not be used as direct clock signals, but as *clock enable* signals.
8575 -- clkgen_i is always synchronous to the main system clock (clk_i).
8676 --
87- -- The following clock dividers are available:
77+ -- The following pre-scaled clock enabled are available:
8878 -- > clkgen_i(clk_div2_c) -> MAIN_CLK/2
8979 -- > clkgen_i(clk_div4_c) -> MAIN_CLK/4
9080 -- > clkgen_i(clk_div8_c) -> MAIN_CLK/8
9686 --
9787 -- For instance, if you want to drive a clock process at MAIN_CLK/8 clock speed you can use the following construct:
9888 --
99- -- if (rstn_i = '0') then -- async and low-active reset (if required at all)
100- -- ...
101- -- elsif rising_edge(clk_i) then -- always use the main clock for all clock processes
89+ -- if rising_edge(clk_i) then -- always use the main clock for all clock processes
10290 -- if (clkgen_i(clk_div8_c) = '1') then -- the div8 "clock" is actually a clock enable
10391 -- ...
10492 -- end if;
10795 -- The clkgen_i input clocks are available when at least one IO/peripheral device (for example UART0) requires the clocks
10896 -- generated by the clock generator. The CFS can enable the clock generator by itself by setting the clkgen_en_o signal high.
10997 -- The CFS cannot ensure to deactivate the clock generator by setting the clkgen_en_o signal low as other peripherals might
110- -- still keep the generator activated. Make sure to deactivate the CFS's clkgen_en_o if no clocks are required in here to
111- -- reduce dynamic power consumption.
98+ -- still keep the generator activated. Make sure to deactivate the CFS's clkgen_en_o if no scaled clocks are required in here
99+ -- to reduce dynamic power consumption.
112100
113101 clkgen_en_o <= '0' ; -- not used for this minimal example
114102
0 commit comments