Activate default clocks on the stm32wb with semaphore

This procedure is preventing the M0 to access the RCC
during the clock enabled by the M4.

Signed-off-by: Francois Ramu <[email protected]>

Author: FRASTM

src/utility/HCISharedMemTransport.cpp

@@ -553,13 +553,35 @@ size_t HCISharedMemTransportClass::write(const uint8_t *data, size_t length)
 //private:
 void HCISharedMemTransportClass::start_ble_rf(void)
 {
-  if ((LL_RCC_IsActiveFlag_PINRST()) && (!LL_RCC_IsActiveFlag_SFTRST())) {
-    /* Simulate power off reset */
-    LL_PWR_EnableBkUpAccess();
-    LL_PWR_EnableBkUpAccess();
-    LL_RCC_ForceBackupDomainReset();
-    LL_RCC_ReleaseBackupDomainReset();
-  }
+	/* HW semaphore Clock is enabled for this variant */
+	LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM);
+
+	/* This prevents the CPU2 (M0+) to configure RCC at the same time */
+	while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID));
+
+#ifdef LL_APB1_GRP1_PERIPH_PWR
+	/* Enable the power interface clock */
+	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
+#endif
+	/* Set the DBP bit in the Power control register 1 (PWR_CR1) */
+	LL_PWR_EnableBkUpAccess();
+
+  /* LSE belongs to the back-up domain, enable access.*/
+  while (!LL_PWR_IsEnabledBkUpAccess()) {
+		/* Wait for Backup domain access */
+	}
+  LL_RCC_ForceBackupDomainReset();
+  LL_RCC_ReleaseBackupDomainReset();
+
+  /* Enable LSE Oscillator (32.768 kHz) */
+	LL_RCC_LSE_Enable();
+	while (!LL_RCC_LSE_IsReady()) {
+		/* Wait for LSE ready */
+	}
+
+	LL_PWR_DisableBkUpAccess();
+
+	LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, 0);
 
   /* Switch OFF LSI as LSE is the source clock */
   LL_RCC_LSI2_Disable();

src/utility/HCISharedMemTransport.h

@@ -25,6 +25,7 @@
 /* STM32WB include files */
 #include "stm32wb55xx.h"
 #include "stm32wbxx_ll_rcc.h"
+#include "stm32wbxx_ll_hsem.h"
 #include "stm32wbxx_ll_ipcc.h"
 #include "stm32wbxx_ll_system.h"
 #include "STM32Cube_FW/tl.h"
@@ -38,6 +39,8 @@
 /* this CONFIG_DEBUG must be defined for -Og option */
 //#define CONFIG_DEBUG
 
+#define CFG_HW_RCC_SEMID                                        3U
+
 /******************************************************************************
  * BLE config parameters
  ******************************************************************************/