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Ruhungmr-c
Ruhung
authored and
mr-c
committed
Revert "neon riscv64: Enable RVV segment load/store only when we have __riscv_zvlsseg flag. (#1285)"
This reverts commit 3e5facc.
1 parent e9cc73d commit 1e16929

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7 files changed

+168
-183
lines changed

7 files changed

+168
-183
lines changed

‎simde/arm/neon/ld2.h‎

Lines changed: 28 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ simde_vld2_s8(int8_t const ptr[HEDLEY_ARRAY_PARAM(16)]) {
5959
simde_vget_high_s8(q)
6060
};
6161
return u;
62-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
62+
#elif defined(SIMDE_RISCV_V_NATIVE)
6363
simde_int8x8_private a_[2];
6464
vint8m1x2_t dest = __riscv_vlseg2e8_v_i8m1x2(&ptr[0], 8);
6565
a_[0].sv64 = __riscv_vget_v_i8m1x2_i8m1(dest, 0);
@@ -102,7 +102,7 @@ simde_int16x4x2_t
102102
simde_vld2_s16(int16_t const ptr[HEDLEY_ARRAY_PARAM(8)]) {
103103
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
104104
return vld2_s16(ptr);
105-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
105+
#elif defined(SIMDE_RISCV_V_NATIVE)
106106
simde_int16x4_private a_[2];
107107
vint16m1x2_t dest = __riscv_vlseg2e16_v_i16m1x2(&ptr[0], 4);
108108
a_[0].sv64 = __riscv_vget_v_i16m1x2_i16m1(dest, 0);
@@ -152,7 +152,7 @@ simde_int32x2x2_t
152152
simde_vld2_s32(int32_t const ptr[HEDLEY_ARRAY_PARAM(4)]) {
153153
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
154154
return vld2_s32(ptr);
155-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
155+
#elif defined(SIMDE_RISCV_V_NATIVE)
156156
simde_int32x2_private a_[2];
157157
vint32m1x2_t dest = __riscv_vlseg2e32_v_i32m1x2(&ptr[0], 2);
158158
a_[0].sv64 = __riscv_vget_v_i32m1x2_i32m1(dest, 0);
@@ -195,7 +195,7 @@ simde_int64x1x2_t
195195
simde_vld2_s64(int64_t const ptr[HEDLEY_ARRAY_PARAM(2)]) {
196196
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
197197
return vld2_s64(ptr);
198-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
198+
#elif defined(SIMDE_RISCV_V_NATIVE)
199199
simde_int64x1_private a_[2];
200200
vint64m1x2_t dest = __riscv_vlseg2e64_v_i64m1x2(&ptr[0], 1);
201201
a_[0].sv64 = __riscv_vget_v_i64m1x2_i64m1(dest, 0);
@@ -249,7 +249,7 @@ simde_vld2_u8(uint8_t const ptr[HEDLEY_ARRAY_PARAM(16)]) {
249249
simde_vget_high_u8(q)
250250
};
251251
return u;
252-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
252+
#elif defined(SIMDE_RISCV_V_NATIVE)
253253
simde_uint8x8_private a_[2];
254254
vuint8m1x2_t dest = __riscv_vlseg2e8_v_u8m1x2(&ptr[0], 8);
255255
a_[0].sv64 = __riscv_vget_v_u8m1x2_u8m1(dest, 0);
@@ -292,7 +292,7 @@ simde_uint16x4x2_t
292292
simde_vld2_u16(uint16_t const ptr[HEDLEY_ARRAY_PARAM(8)]) {
293293
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
294294
return vld2_u16(ptr);
295-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
295+
#elif defined(SIMDE_RISCV_V_NATIVE)
296296
simde_uint16x4_private a_[2];
297297
vuint16m1x2_t dest = __riscv_vlseg2e16_v_u16m1x2(&ptr[0], 4);
298298
a_[0].sv64 = __riscv_vget_v_u16m1x2_u16m1(dest, 0);
@@ -342,7 +342,7 @@ simde_uint32x2x2_t
342342
simde_vld2_u32(uint32_t const ptr[HEDLEY_ARRAY_PARAM(4)]) {
343343
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
344344
return vld2_u32(ptr);
345-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
345+
#elif defined(SIMDE_RISCV_V_NATIVE)
346346
simde_uint32x2_private a_[2];
347347
vuint32m1x2_t dest = __riscv_vlseg2e32_v_u32m1x2(&ptr[0], 2);
348348
a_[0].sv64 = __riscv_vget_v_u32m1x2_u32m1(dest, 0);
@@ -385,7 +385,7 @@ simde_uint64x1x2_t
385385
simde_vld2_u64(uint64_t const ptr[HEDLEY_ARRAY_PARAM(2)]) {
386386
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
387387
return vld2_u64(ptr);
388-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
388+
#elif defined(SIMDE_RISCV_V_NATIVE)
389389
simde_uint64x1_private a_[2];
390390
vuint64m1x2_t dest = __riscv_vlseg2e64_v_u64m1x2(&ptr[0], 1);
391391
a_[0].sv64 = __riscv_vget_v_u64m1x2_u64m1(dest, 0);
@@ -428,8 +428,7 @@ simde_float16x4x2_t
428428
simde_vld2_f16(simde_float16_t const ptr[HEDLEY_ARRAY_PARAM(8)]) {
429429
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
430430
return vld2_f16(ptr);
431-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG) \
432-
&& SIMDE_ARCH_RISCV_ZVFH && (SIMDE_NATURAL_VECTOR_SIZE >= 128)
431+
#elif defined(SIMDE_RISCV_V_NATIVE) && SIMDE_ARCH_RISCV_ZVFH && (SIMDE_NATURAL_VECTOR_SIZE >= 128)
433432
simde_float16x4_private r_[2];
434433
vfloat16m1x2_t dest = __riscv_vlseg2e16_v_f16m1x2((_Float16 *)&ptr[0], 4);
435434
r_[0].sv64 = __riscv_vget_v_f16m1x2_f16m1(dest, 0);
@@ -467,7 +466,7 @@ simde_float32x2x2_t
467466
simde_vld2_f32(simde_float32_t const ptr[HEDLEY_ARRAY_PARAM(4)]) {
468467
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
469468
return vld2_f32(ptr);
470-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
469+
#elif defined(SIMDE_RISCV_V_NATIVE)
471470
simde_float32x2_private r_[2];
472471
vfloat32m1x2_t dest = __riscv_vlseg2e32_v_f32m1x2(&ptr[0], 2);
473472
r_[0].sv64 = __riscv_vget_v_f32m1x2_f32m1(dest, 0);
@@ -510,7 +509,7 @@ simde_float64x1x2_t
510509
simde_vld2_f64(simde_float64_t const ptr[HEDLEY_ARRAY_PARAM(2)]) {
511510
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
512511
return vld2_f64(ptr);
513-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
512+
#elif defined(SIMDE_RISCV_V_NATIVE)
514513
simde_float64x1_private r_[2];
515514
vfloat64m1x2_t dest = __riscv_vlseg2e64_v_f64m1x2(&ptr[0], 1);
516515
r_[0].sv64 = __riscv_vget_v_f64m1x2_f64m1(dest, 0);
@@ -553,7 +552,7 @@ simde_int8x16x2_t
553552
simde_vld2q_s8(int8_t const ptr[HEDLEY_ARRAY_PARAM(32)]) {
554553
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
555554
return vld2q_s8(ptr);
556-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
555+
#elif defined(SIMDE_RISCV_V_NATIVE)
557556
simde_int8x16_private a_[2];
558557
vint8m1x2_t dest = __riscv_vlseg2e8_v_i8m1x2(&ptr[0], 16);
559558
a_[0].sv128 = __riscv_vget_v_i8m1x2_i8m1(dest, 0);
@@ -603,7 +602,7 @@ simde_int32x4x2_t
603602
simde_vld2q_s32(int32_t const ptr[HEDLEY_ARRAY_PARAM(8)]) {
604603
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
605604
return vld2q_s32(ptr);
606-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
605+
#elif defined(SIMDE_RISCV_V_NATIVE)
607606
simde_int32x4_private a_[2];
608607
vint32m1x2_t dest = __riscv_vlseg2e32_v_i32m1x2(&ptr[0], 4);
609608
a_[0].sv128 = __riscv_vget_v_i32m1x2_i32m1(dest, 0);
@@ -653,7 +652,7 @@ simde_int16x8x2_t
653652
simde_vld2q_s16(int16_t const ptr[HEDLEY_ARRAY_PARAM(16)]) {
654653
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
655654
return vld2q_s16(ptr);
656-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
655+
#elif defined(SIMDE_RISCV_V_NATIVE)
657656
simde_int16x8_private r_[2];
658657
vint16m1x2_t dest = __riscv_vlseg2e16_v_i16m1x2(&ptr[0], 8);
659658
r_[0].sv128 = __riscv_vget_v_i16m1x2_i16m1(dest, 0);
@@ -703,7 +702,7 @@ simde_int64x2x2_t
703702
simde_vld2q_s64(int64_t const ptr[HEDLEY_ARRAY_PARAM(4)]) {
704703
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
705704
return vld2q_s64(ptr);
706-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
705+
#elif defined(SIMDE_RISCV_V_NATIVE)
707706
simde_int64x2_private r_[2];
708707
vint64m1x2_t dest = __riscv_vlseg2e64_v_i64m1x2(&ptr[0], 2);
709708
r_[0].sv128 = __riscv_vget_v_i64m1x2_i64m1(dest, 0);
@@ -740,7 +739,7 @@ simde_uint8x16x2_t
740739
simde_vld2q_u8(uint8_t const ptr[HEDLEY_ARRAY_PARAM(32)]) {
741740
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
742741
return vld2q_u8(ptr);
743-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
742+
#elif defined(SIMDE_RISCV_V_NATIVE)
744743
simde_uint8x16_private r_[2];
745744
vuint8m1x2_t dest = __riscv_vlseg2e8_v_u8m1x2(&ptr[0], 16);
746745
r_[0].sv128 = __riscv_vget_v_u8m1x2_u8m1(dest, 0);
@@ -790,7 +789,7 @@ simde_uint16x8x2_t
790789
simde_vld2q_u16(uint16_t const ptr[HEDLEY_ARRAY_PARAM(16)]) {
791790
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
792791
return vld2q_u16(ptr);
793-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
792+
#elif defined(SIMDE_RISCV_V_NATIVE)
794793
simde_uint16x8_private r_[2];
795794
vuint16m1x2_t dest = __riscv_vlseg2e16_v_u16m1x2(&ptr[0], 8);
796795
r_[0].sv128 = __riscv_vget_v_u16m1x2_u16m1(dest, 0);
@@ -840,7 +839,7 @@ simde_uint32x4x2_t
840839
simde_vld2q_u32(uint32_t const ptr[HEDLEY_ARRAY_PARAM(8)]) {
841840
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
842841
return vld2q_u32(ptr);
843-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
842+
#elif defined(SIMDE_RISCV_V_NATIVE)
844843
simde_uint32x4_private r_[2];
845844
vuint32m1x2_t dest = __riscv_vlseg2e32_v_u32m1x2(&ptr[0], 4);
846845
r_[0].sv128 = __riscv_vget_v_u32m1x2_u32m1(dest, 0);
@@ -890,7 +889,7 @@ simde_uint64x2x2_t
890889
simde_vld2q_u64(uint64_t const ptr[HEDLEY_ARRAY_PARAM(4)]) {
891890
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
892891
return vld2q_u64(ptr);
893-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
892+
#elif defined(SIMDE_RISCV_V_NATIVE)
894893
simde_uint64x2_private r_[2];
895894
vuint64m1x2_t dest = __riscv_vlseg2e64_v_u64m1x2(&ptr[0], 2);
896895
r_[0].sv128 = __riscv_vget_v_u64m1x2_u64m1(dest, 0);
@@ -927,8 +926,7 @@ simde_float16x8x2_t
927926
simde_vld2q_f16(simde_float16_t const ptr[HEDLEY_ARRAY_PARAM(16)]) {
928927
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
929928
return vld2q_f16(ptr);
930-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG) \
931-
&& SIMDE_ARCH_RISCV_ZVFH && (SIMDE_NATURAL_VECTOR_SIZE >= 128)
929+
#elif defined(SIMDE_RISCV_V_NATIVE) && SIMDE_ARCH_RISCV_ZVFH && (SIMDE_NATURAL_VECTOR_SIZE >= 128)
932930
simde_float16x8_private r_[2];
933931
vfloat16m1x2_t dest = __riscv_vlseg2e16_v_f16m1x2((_Float16 *)&ptr[0], 8);
934932
r_[0].sv128 = __riscv_vget_v_f16m1x2_f16m1(dest, 0);
@@ -973,7 +971,7 @@ simde_float32x4x2_t
973971
simde_vld2q_f32(simde_float32_t const ptr[HEDLEY_ARRAY_PARAM(8)]) {
974972
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
975973
return vld2q_f32(ptr);
976-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
974+
#elif defined(SIMDE_RISCV_V_NATIVE)
977975
simde_float32x4_private r_[2];
978976
vfloat32m1x2_t dest = __riscv_vlseg2e32_v_f32m1x2(&ptr[0], 4);
979977
r_[0].sv128 = __riscv_vget_v_f32m1x2_f32m1(dest, 0);
@@ -1023,7 +1021,7 @@ simde_float64x2x2_t
10231021
simde_vld2q_f64(simde_float64_t const ptr[HEDLEY_ARRAY_PARAM(4)]) {
10241022
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
10251023
return vld2q_f64(ptr);
1026-
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
1024+
#elif defined(SIMDE_RISCV_V_NATIVE)
10271025
simde_float64x2_private r_[2];
10281026
vfloat64m1x2_t dest = __riscv_vlseg2e64_v_f64m1x2(&ptr[0], 2);
10291027
r_[0].sv128 = __riscv_vget_v_f64m1x2_f64m1(dest, 0);
@@ -1062,7 +1060,7 @@ simde_vld2_p8(simde_poly8_t const ptr[HEDLEY_ARRAY_PARAM(16)]) {
10621060
return vld2_p8(ptr);
10631061
#else
10641062
simde_poly8x8_private r_[2];
1065-
#if defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
1063+
#if defined(SIMDE_RISCV_V_NATIVE)
10661064
vuint8m1x2_t dest = __riscv_vlseg2e8_v_u8m1x2(&ptr[0], 8);
10671065
r_[0].sv64 = __riscv_vget_v_u8m1x2_u8m1(dest, 0);
10681066
r_[1].sv64 = __riscv_vget_v_u8m1x2_u8m1(dest, 1);
@@ -1097,7 +1095,7 @@ simde_vld2_p16(simde_poly16_t const ptr[HEDLEY_ARRAY_PARAM(8)]) {
10971095
SIMDE_DIAGNOSTIC_DISABLE_UNINITIALIZED_
10981096
#endif
10991097
simde_poly16x4_private r_[2];
1100-
#if defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
1098+
#if defined(SIMDE_RISCV_V_NATIVE)
11011099
vuint16m1x2_t dest = __riscv_vlseg2e16_v_u16m1x2(&ptr[0], 4);
11021100
r_[0].sv64 = __riscv_vget_v_u16m1x2_u16m1(dest, 0);
11031101
r_[1].sv64 = __riscv_vget_v_u16m1x2_u16m1(dest, 1);
@@ -1137,7 +1135,7 @@ simde_vld2_p64(simde_poly64_t const ptr[HEDLEY_ARRAY_PARAM(2)]) {
11371135
#endif
11381136
simde_poly64x1_private r_[2];
11391137

1140-
#if defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
1138+
#if defined(SIMDE_RISCV_V_NATIVE)
11411139
vuint64m1x2_t dest = __riscv_vlseg2e64_v_u64m1x2(&ptr[0], 1);
11421140
r_[0].sv64 = __riscv_vget_v_u64m1x2_u64m1(dest, 0);
11431141
r_[1].sv64 = __riscv_vget_v_u64m1x2_u64m1(dest, 1);
@@ -1177,7 +1175,7 @@ simde_vld2q_p8(simde_poly8_t const ptr[HEDLEY_ARRAY_PARAM(32)]) {
11771175
#endif
11781176
simde_poly8x16_private r_[2];
11791177

1180-
#if defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
1178+
#if defined(SIMDE_RISCV_V_NATIVE)
11811179
vuint8m1x2_t dest = __riscv_vlseg2e8_v_u8m1x2(&ptr[0], 16);
11821180
r_[0].sv128 = __riscv_vget_v_u8m1x2_u8m1(dest, 0);
11831181
r_[1].sv128 = __riscv_vget_v_u8m1x2_u8m1(dest, 1);
@@ -1217,7 +1215,7 @@ simde_vld2q_p16(simde_poly16_t const ptr[HEDLEY_ARRAY_PARAM(16)]) {
12171215
#endif
12181216
simde_poly16x8_private r_[2];
12191217

1220-
#if defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
1218+
#if defined(SIMDE_RISCV_V_NATIVE)
12211219
vuint16m1x2_t dest = __riscv_vlseg2e16_v_u16m1x2(&ptr[0], 8);
12221220
r_[0].sv128 = __riscv_vget_v_u16m1x2_u16m1(dest, 0);
12231221
r_[1].sv128 = __riscv_vget_v_u16m1x2_u16m1(dest, 1);
@@ -1253,7 +1251,7 @@ simde_vld2q_p64(simde_poly64_t const ptr[HEDLEY_ARRAY_PARAM(4)]) {
12531251
#else
12541252
simde_poly64x2_private r_[2];
12551253

1256-
#if defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVLSSEG)
1254+
#if defined(SIMDE_RISCV_V_NATIVE)
12571255
vuint64m1x2_t dest = __riscv_vlseg2e64_v_u64m1x2(&ptr[0], 2);
12581256
r_[0].sv128 = __riscv_vget_v_u64m1x2_u64m1(dest, 0);
12591257
r_[1].sv128 = __riscv_vget_v_u64m1x2_u64m1(dest, 1);

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