|
25 | 25 | #include "fuse.h" |
26 | 26 |
|
27 | 27 |
|
28 | | -static const struct tegra_emc_table Nakasi_dvfs_Elpida_table_0430[] = { |
| 28 | +static const struct tegra_emc_table Nakasi_dvfs_Elpida_table_0704_15R7[] = { |
29 | 29 | { |
30 | 30 | 0x32, /* Rev 3.2 */ |
31 | 31 | 25500, /* SDRAM frequency */ |
@@ -117,7 +117,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Elpida_table_0430[] = { |
117 | 117 | 0x00000000, /* EMC_CTT */ |
118 | 118 | 0x00000000, /* EMC_CTT_DURATION */ |
119 | 119 | 0x80000287, /* EMC_DYN_SELF_REF_CONTROL */ |
120 | | - 0x00020001, /* MC_EMEM_ARB_CFG */ |
| 120 | + 0x00030003, /* MC_EMEM_ARB_CFG */ |
121 | 121 | 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */ |
122 | 122 | 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ |
123 | 123 | 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ |
@@ -237,7 +237,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Elpida_table_0430[] = { |
237 | 237 | 0x00000000, /* EMC_CTT */ |
238 | 238 | 0x00000000, /* EMC_CTT_DURATION */ |
239 | 239 | 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */ |
240 | | - 0x00010001, /* MC_EMEM_ARB_CFG */ |
| 240 | + 0x00010003, /* MC_EMEM_ARB_CFG */ |
241 | 241 | 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */ |
242 | 242 | 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ |
243 | 243 | 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ |
@@ -357,7 +357,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Elpida_table_0430[] = { |
357 | 357 | 0x00000000, /* EMC_CTT */ |
358 | 358 | 0x00000000, /* EMC_CTT_DURATION */ |
359 | 359 | 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ |
360 | | - 0x00000001, /* MC_EMEM_ARB_CFG */ |
| 360 | + 0x00000003, /* MC_EMEM_ARB_CFG */ |
361 | 361 | 0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */ |
362 | 362 | 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ |
363 | 363 | 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ |
@@ -477,7 +477,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Elpida_table_0430[] = { |
477 | 477 | 0x00000000, /* EMC_CTT */ |
478 | 478 | 0x00000000, /* EMC_CTT_DURATION */ |
479 | 479 | 0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */ |
480 | | - 0x00000003, /* MC_EMEM_ARB_CFG */ |
| 480 | + 0x00000006, /* MC_EMEM_ARB_CFG */ |
481 | 481 | 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */ |
482 | 482 | 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ |
483 | 483 | 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ |
@@ -597,7 +597,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Elpida_table_0430[] = { |
597 | 597 | 0x00000000, /* EMC_CTT */ |
598 | 598 | 0x00000000, /* EMC_CTT_DURATION */ |
599 | 599 | 0x800014d4, /* EMC_DYN_SELF_REF_CONTROL */ |
600 | | - 0x00000005, /* MC_EMEM_ARB_CFG */ |
| 600 | + 0x0000000a, /* MC_EMEM_ARB_CFG */ |
601 | 601 | 0xc000003d, /* MC_EMEM_ARB_OUTSTANDING_REQ */ |
602 | 602 | 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ |
603 | 603 | 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ |
@@ -717,7 +717,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Elpida_table_0430[] = { |
717 | 717 | 0x00000000, /* EMC_CTT */ |
718 | 718 | 0x00000000, /* EMC_CTT_DURATION */ |
719 | 719 | 0x800028a5, /* EMC_DYN_SELF_REF_CONTROL */ |
720 | | - 0x0000000a, /* MC_EMEM_ARB_CFG */ |
| 720 | + 0x00000014, /* MC_EMEM_ARB_CFG */ |
721 | 721 | 0xc0000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */ |
722 | 722 | 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */ |
723 | 723 | 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ |
@@ -748,7 +748,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Elpida_table_0430[] = { |
748 | 748 | }, |
749 | 749 | }; |
750 | 750 |
|
751 | | -static const struct tegra_emc_table Nakasi_dvfs_Hynix_table_0430[] ={ |
| 751 | +static const struct tegra_emc_table Nakasi_dvfs_Hynix_table_0704_15R7[] = { |
752 | 752 | { |
753 | 753 | 0x32, /* Rev 3.2 */ |
754 | 754 | 25500, /* SDRAM frequency */ |
@@ -840,7 +840,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Hynix_table_0430[] ={ |
840 | 840 | 0x00000000, /* EMC_CTT */ |
841 | 841 | 0x00000000, /* EMC_CTT_DURATION */ |
842 | 842 | 0x80000287, /* EMC_DYN_SELF_REF_CONTROL */ |
843 | | - 0x00020001, /* MC_EMEM_ARB_CFG */ |
| 843 | + 0x00030003, /* MC_EMEM_ARB_CFG */ |
844 | 844 | 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */ |
845 | 845 | 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ |
846 | 846 | 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ |
@@ -960,7 +960,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Hynix_table_0430[] ={ |
960 | 960 | 0x00000000, /* EMC_CTT */ |
961 | 961 | 0x00000000, /* EMC_CTT_DURATION */ |
962 | 962 | 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */ |
963 | | - 0x00010001, /* MC_EMEM_ARB_CFG */ |
| 963 | + 0x00010003, /* MC_EMEM_ARB_CFG */ |
964 | 964 | 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */ |
965 | 965 | 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ |
966 | 966 | 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ |
@@ -1080,7 +1080,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Hynix_table_0430[] ={ |
1080 | 1080 | 0x00000000, /* EMC_CTT */ |
1081 | 1081 | 0x00000000, /* EMC_CTT_DURATION */ |
1082 | 1082 | 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ |
1083 | | - 0x00000001, /* MC_EMEM_ARB_CFG */ |
| 1083 | + 0x00000003, /* MC_EMEM_ARB_CFG */ |
1084 | 1084 | 0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */ |
1085 | 1085 | 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ |
1086 | 1086 | 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ |
@@ -1200,7 +1200,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Hynix_table_0430[] ={ |
1200 | 1200 | 0x00000000, /* EMC_CTT */ |
1201 | 1201 | 0x00000000, /* EMC_CTT_DURATION */ |
1202 | 1202 | 0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */ |
1203 | | - 0x00000003, /* MC_EMEM_ARB_CFG */ |
| 1203 | + 0x00000006, /* MC_EMEM_ARB_CFG */ |
1204 | 1204 | 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */ |
1205 | 1205 | 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ |
1206 | 1206 | 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ |
@@ -1320,7 +1320,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Hynix_table_0430[] ={ |
1320 | 1320 | 0x00000000, /* EMC_CTT */ |
1321 | 1321 | 0x00000000, /* EMC_CTT_DURATION */ |
1322 | 1322 | 0x800014d4, /* EMC_DYN_SELF_REF_CONTROL */ |
1323 | | - 0x00000005, /* MC_EMEM_ARB_CFG */ |
| 1323 | + 0x0000000a, /* MC_EMEM_ARB_CFG */ |
1324 | 1324 | 0xc000003d, /* MC_EMEM_ARB_OUTSTANDING_REQ */ |
1325 | 1325 | 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ |
1326 | 1326 | 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ |
@@ -1440,7 +1440,7 @@ static const struct tegra_emc_table Nakasi_dvfs_Hynix_table_0430[] ={ |
1440 | 1440 | 0x00000000, /* EMC_CTT */ |
1441 | 1441 | 0x00000000, /* EMC_CTT_DURATION */ |
1442 | 1442 | 0x800028a5, /* EMC_DYN_SELF_REF_CONTROL */ |
1443 | | - 0x0000000a, /* MC_EMEM_ARB_CFG */ |
| 1443 | + 0x00000014, /* MC_EMEM_ARB_CFG */ |
1444 | 1444 | 0xc0000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */ |
1445 | 1445 | 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */ |
1446 | 1446 | 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ |
@@ -1514,24 +1514,24 @@ int grouper_emc_init(void) |
1514 | 1514 | printk("grouper_emc_init:mem_bootstrap_ad4=%u mem_bootstrap_ad5=%u \n",mem_bootstrap_ad4,mem_bootstrap_ad5); |
1515 | 1515 |
|
1516 | 1516 | if(!mem_bootstrap_ad4 && !mem_bootstrap_ad5){ |
1517 | | - tegra_init_emc(Nakasi_dvfs_Elpida_table_0430, |
1518 | | - ARRAY_SIZE(Nakasi_dvfs_Elpida_table_0430)); |
1519 | | - printk("grouper_emc_init:Nakasi_dvfs_Elpida_table_0430\n"); |
| 1517 | + tegra_init_emc(Nakasi_dvfs_Elpida_table_0704_15R7, |
| 1518 | + ARRAY_SIZE(Nakasi_dvfs_Elpida_table_0704_15R7)); |
| 1519 | + printk("grouper_emc_init:Nakasi_dvfs_Elpida_table_0704_15R7\n"); |
1520 | 1520 | }else{ |
1521 | | - tegra_init_emc(Nakasi_dvfs_Hynix_table_0430, |
1522 | | - ARRAY_SIZE(Nakasi_dvfs_Hynix_table_0430)); |
1523 | | - printk("grouper_emc_init:Nakasi_dvfs_Hynix_table_0430\n"); |
| 1521 | + tegra_init_emc(Nakasi_dvfs_Hynix_table_0704_15R7, |
| 1522 | + ARRAY_SIZE(Nakasi_dvfs_Hynix_table_0704_15R7)); |
| 1523 | + printk("grouper_emc_init:Nakasi_dvfs_Hynix_table_0704_15R7\n"); |
1524 | 1524 | } |
1525 | 1525 |
|
1526 | 1526 | return 0; |
1527 | 1527 |
|
1528 | 1528 | err_handle: |
1529 | | - if(tegra_init_emc(Nakasi_dvfs_Elpida_table_0430, |
1530 | | - ARRAY_SIZE(Nakasi_dvfs_Elpida_table_0430))){ |
1531 | | - printk("[unknow bootstrap pin] use Nakasi_dvfs_Elpida_table_0430\n"); |
1532 | | - }else if (tegra_init_emc(Nakasi_dvfs_Hynix_table_0430, |
1533 | | - ARRAY_SIZE(Nakasi_dvfs_Hynix_table_0430))){ |
1534 | | - printk("[unknow bootstrap pin] use Nakasi_dvfs_Hynix_table_0430 \n"); |
| 1529 | + if(tegra_init_emc(Nakasi_dvfs_Elpida_table_0704_15R7, |
| 1530 | + ARRAY_SIZE(Nakasi_dvfs_Elpida_table_0704_15R7))){ |
| 1531 | + printk("[unknow bootstrap pin] use Nakasi_dvfs_Elpida_table_0704_15R7\n"); |
| 1532 | + }else if (tegra_init_emc(Nakasi_dvfs_Hynix_table_0704_15R7, |
| 1533 | + ARRAY_SIZE(Nakasi_dvfs_Hynix_table_0704_15R7))){ |
| 1534 | + printk("[unknow bootstrap pin] use Nakasi_dvfs_Hynix_table_0704_15R7\n"); |
1535 | 1535 | }else |
1536 | 1536 | printk("grouper_emc_init:no validate EMC tabe, disable EMC DVFS\n"); |
1537 | 1537 | return 0; |
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