finalized manually-written file and fixed minor issue in compressed register operands generation

Author: moste00

lib/c_codegen/ccodegen_operand_info.ml

@@ -14,7 +14,9 @@ let single_operand_to_c index operand walker =
         match regfile with
         | Base -> "AS_GEN_PURPOSE_REG"
         | Float_or_Double -> "AS_FLOAT_REG"
-        | Base_or_Float -> "AS_GEN_PURPOSE_REG"
+        (* assume the compressed register is a general purpose register, true for most cases *)
+        (* float cases will be patched manually later *)
+        | Base_or_Float -> "AS_COMPRESSED_GEN_PURPOSE_REG"
         | Vector -> "AS_VECTOR_REG"
       in
       let op_indexing = "ops[" ^ string_of_int index ^ "]" in

riscv_disasm/RISCVAst2StrHelpers.h

@@ -130,7 +130,7 @@ DEF_HEX_BITS_SIGNED(30);
 DEF_HEX_BITS_SIGNED(31);
 DEF_HEX_BITS_SIGNED(32);
 
-const static const char *reg_names[] = {
+const static char *reg_names[] = {
     "zero", "ra", "sp", "gp", "tp",  "t0",  "t1", "t2", "fp", "s1", "a0",
     "a1",   "a2", "a3", "a4", "a5",  "a6",  "a7", "s2", "s3", "s4", "s5",
     "s6",   "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"};
@@ -139,14 +139,14 @@ static inline void reg_name(uint8_t r, SStream *ss, RVContext *ctx) {
   SStream_concat(ss, reg_names[r]);
 }
 
-const static const char *creg_names[] = {"s0", "s1", "a0", "a1",
+const static char *creg_names[] = {"s0", "s1", "a0", "a1",
                                          "a2", "a3", "a4", "a5"};
 static inline void creg_name(uint8_t r, SStream *ss, RVContext *ctx) {
   CS_ASSERT(r < 8);
   SStream_concat(ss, creg_names[r]);
 }
 
-const static const char *freg_names[] = {
+const static char *freg_names[] = {
     "ft0", "ft1", "ft2",  "ft3",  "ft4", "ft5", "ft6",  "ft7",
     "fs0", "fs1", "fa0",  "fa1",  "fa2", "fa3", "fa4",  "fa5",
     "fa6", "fa7", "fs2",  "fs3",  "fs4", "fs5", "fs6",  "fs7",
@@ -156,7 +156,7 @@ static inline void freg_name(uint8_t r, SStream *ss, RVContext *ctx) {
   SStream_concat(ss, freg_names[r]);
 }
 
-const static const char *vreg_names[] = {
+const static char *vreg_names[] = {
     "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",  "v8",  "v9",  "v10",
     "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
     "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"};

riscv_disasm/RISCVDecodeHelpers.h

@@ -248,7 +248,8 @@ static inline bool currentlyEnabled(ExtensionType t, RVContext *ctx) {
   case RISCV_Ext_Svpbmt:
     return 0;
   case RISCV_Ext_Sscofpmf:
-    return HART_SUPPORTS(Ext_Sscofpmf) && currentlyEnabled(RISCV_Ext_Zihpm, ctx);
+    return HART_SUPPORTS(Ext_Sscofpmf) &&
+           currentlyEnabled(RISCV_Ext_Zihpm, ctx);
   case RISCV_Ext_Smcntrpmf:
     return HART_SUPPORTS(Ext_Smcntrpmf) &&
            currentlyEnabled(RISCV_Ext_Zicntr, ctx);
@@ -348,13 +349,13 @@ static inline bool validDoubleRegs2(uint8_t rs1, uint8_t rd, RVContext *ctx) {
 }
 
 static inline bool validDoubleRegs3(uint8_t rs2, uint8_t rs1, uint8_t rd,
-                                      RVContext *ctx) {
+                                    RVContext *ctx) {
   uint8_t regs[] = {rs2, rs1, rd, 0xFF};
   return validDoubleRegsN(regs, ctx);
 }
 
 static inline bool validDoubleRegs4(uint8_t rs3, uint8_t rs2, uint8_t rs1,
-                                      uint8_t rd, RVContext *ctx) {
+                                    uint8_t rd, RVContext *ctx) {
   uint8_t regs[] = {rs3, rs2, rs1, rd, 0xFF};
   return validDoubleRegsN(regs, ctx);
 }
@@ -409,19 +410,18 @@ static inline float get_lmul(int32_t lpow) {
   return (float)(~0);
 }
 
-static inline bool zvk_check_encdec(int32_t egw, int32_t egs,
-                                      RVContext *ctx) {
+static inline bool zvk_check_encdec(int32_t egw, int32_t egs, RVContext *ctx) {
   return (ctx->vl % egs == 0) && (ctx->vstart % egs == 0) &&
          (get_lmul(get_lmul_pow(ctx)) * ctx->vlen >= egw);
 }
 
 static inline bool zvk_valid_reg_overlap(uint8_t rs, uint8_t rd,
-                                           int32_t emul_pow) {
+                                         int32_t emul_pow) {
   uint64_t reg_group_size = (emul_pow > 0) ? 1 << emul_pow : 1;
   return (rs + reg_group_size <= rd) || (rd + reg_group_size <= rs);
 }
 static inline bool zvknhab_check_encdec(uint8_t vs2, uint8_t vs1, uint8_t vd,
-                                          RVContext *ctx) {
+                                        RVContext *ctx) {
   uint32_t sew = get_sew(ctx);
   int32_t lmulpow = get_lmul_pow(ctx);
   return zvk_check_encdec(sew, 4, ctx) &&