Merge branch 'dev' into m_interrupts

Signed-off-by: Umer Shahid <[email protected]>

Author: UmerShahidengr

.github/workflows/coverage.yml

@@ -108,7 +108,7 @@ jobs:
         uses: actions/cache/restore@v4
         with:
           path: ${{ github.workspace }}/sail
-          key: sail-${{ env.SAIL_HASH }}-RV${{ matrix.xlen }}
+          key: sail-${{ env.SAIL_HASH }}
 
       - name: Install Sail
         if: steps.cache-sail-restore.outputs.cache-hit != 'true'
@@ -120,7 +120,7 @@ jobs:
           cmake -S . -B build -DCMAKE_BUILD_TYPE=RelWithDebInfo -GNinja
           cmake --build build
           mkdir -p $GITHUB_WORKSPACE/sail
-          mv build/c_emulator/riscv_sim_rv${{ matrix.xlen }}d $GITHUB_WORKSPACE/sail/riscv_sim_rv${{ matrix.xlen }}d
+          mv build/c_emulator/sail_riscv_sim $GITHUB_WORKSPACE/sail/sail_riscv_sim
 
       - name: Save cached Sail
         if: steps.cache-sail-restore.outputs.cache-hit != 'true'

.github/workflows/test.yml

@@ -117,7 +117,7 @@ jobs:
         uses: actions/cache/restore@v4
         with:
           path: ${{ github.workspace }}/sail
-          key: sail-${{ env.SAIL_HASH }}-RV${{ matrix.xlen }}
+          key: sail-${{ env.SAIL_HASH }}
 
       - name: Install Sail
         if: steps.cache-sail-restore.outputs.cache-hit != 'true'
@@ -129,7 +129,7 @@ jobs:
           cmake -S . -B build -DCMAKE_BUILD_TYPE=RelWithDebInfo -GNinja
           cmake --build build
           mkdir -p $GITHUB_WORKSPACE/sail
-          mv build/c_emulator/riscv_sim_rv${{ matrix.xlen }}d $GITHUB_WORKSPACE/sail/riscv_sim_rv${{ matrix.xlen }}d
+          mv build/c_emulator/sail_riscv_sim $GITHUB_WORKSPACE/sail/sail_riscv_sim
 
       - name: Save cached Sail
         if: steps.cache-sail-restore.outputs.cache-hit != 'true'

README.md

@@ -220,10 +220,10 @@ Then build the RISC-V Sail Model:
 ```bash
 $ git clone https://github.com/riscv/sail-riscv.git
 $ cd sail-riscv
-$ ./build-simulators.sh
+$ ./build_simulators.sh
 ```
 
-This will create a C simulator in `build/c_emulator/riscv_sim_rv64d` and `build/c_emulator/riscv_sim_rv32d`. You will need to add this path to your `$PATH` or create an alias to execute them from the command line.
+This will create a C simulator in `build/c_emulator/sail_riscv_sim`. You will need to add this path to your `$PATH` or create an alias to execute it from the command line.
 
 
 ## Necessary Env Files

coverage/b/rv32i_b.cgf

@@ -90,7 +90,7 @@ zext.h_32:
     mnemonics: 
       zext.h: 0
     base_op: pack
-    p_op_cond: rs2 == x0
+    p_op_cond: rs2 == "x0"
     rs1: 
       <<: *all_regs
     rd: 

coverage/b/rv64i_b.cgf

@@ -191,7 +191,7 @@ zext.h_64:
     mnemonics: 
       zext.h: 0
     base_op: packw
-    p_op_cond: rs2 == x0
+    p_op_cond: rs2 == "x0"
     rs1: 
       <<: *all_regs
     rd: 

coverage/c/rv32ic.cgf

@@ -401,13 +401,6 @@ cjr:
     c.jr: 0
   rs1:
     <<: *all_regs_mx0
-  op_comb:
-    <<: *sfmt_op_comb
-  val_comb:
-    <<: *base_rs1val_sgn_rs2val_zero
-    abstract_comb:
-      'sp_dataset(xlen)': 0
-      <<: *rs1val_walking
 
 cmv:
     config: 
@@ -451,13 +444,6 @@ cjalr:
     c.jalr: 0
   rs1:
     <<: *all_regs_mx0
-  op_comb:
-    <<: *sfmt_op_comb
-  val_comb:
-    <<: *base_rs1val_sgn_rs2val_zero
-    abstract_comb:
-      'sp_dataset(xlen)': 0
-      <<: *rs1val_walking
 
 cswsp:
     config: 

coverage/c/rv64ic.cgf

@@ -493,13 +493,6 @@ cjr:
     c.jr: 0
   rs1:
     <<: *all_regs_mx0
-  op_comb:
-    <<: *sfmt_op_comb
-  val_comb:
-    <<: *base_rs1val_sgn_rs2val_zero
-    abstract_comb:
-      'sp_dataset(xlen)': 0
-      <<: *rs1val_walking
 
 cmv:
     config: 
@@ -543,13 +536,6 @@ cjalr:
     c.jalr: 0
   rs1:
     <<: *all_regs_mx0
-  op_comb:
-    <<: *sfmt_op_comb
-  val_comb:
-    <<: *base_rs1val_sgn_rs2val_zero
-    abstract_comb:
-      'sp_dataset(xlen)': 0
-      <<: *rs1val_walking
 
 cswsp:
     config: 

coverage/header_file.yaml

@@ -916,6 +916,24 @@ common:
  RISCV_PGSIZE: (1 << RISCV_PGSHIFT)
 
 PMP_MACROS:
+ PMPCFG_BIT_SET: 1
+ PMPCFG_BIT_NOT_SET: 0
+ PMPCFG_ONLY_R_SET: 0x01
+ PMPCFG_ONLY_X_SET: 0x04
+ PMPCFG_ONLY_RW_SET: 0x03
+ PMPCFG_ONLY_RX_SET: 0x05
+ PMPCFG_ONLY_RWX_SET: 0x07
+ PMPCFG_OFF_MODE: 0x00
+ PMPCFG_TOR_MODE: 0x08
+ PMPCFG_NA4_MODE: 0x10
+ PMPCFG_NAPOT_MODE: 0x18
+ PMPCFG_R_BIT: 0x01
+ PMPCFG_W_BIT: 0x02
+ PMPCFG_X_BIT: 0x04
+ PMPCFG_RWX_BIT: 0x07
+ PMPCFG_A_BIT: 0x18
+ PMPCFG_RW_BIT: 0x60
+ PMPCFG_L_BIT: 0x80
  PMP0_CFG_SHIFT: 0
  PMP1_CFG_SHIFT: 8
  PMP2_CFG_SHIFT: 16

coverage/pmp/rv32_pmp.cgf

@@ -7,8 +7,8 @@ pmp_cfg_locked_write_unrelated:
     "{csrrs, csrrw}" : 0
   csr_comb:
     # (Lock bit set) and (req) and (old_value_pmpcfg != 0)
-    (pmpcfg{{0 ... 15} >> 2} >> {0, 8, 16, 24}{[$2%4]} & 0x80 == 0x80) and (((old("pmpcfg$2") ^ pmpcfg$2) >> $3 & 0xFF) == 0x00) and old("pmpcfg$2") != 0: 0 
-    (pmpcfg{{0 ... 15} >> 2} >> {0, 8, 16, 24}{[$1%4]} & 0x80 == 0x80) and (old("pmpaddr$1") == (pmpaddr$1)) and (pmpcfg$2 != 0): 0
+    (pmpcfg{{0 ... 15} >> 2} >> {0, 8, 16, 24}{[$2%4]} & 0x80 == 0x80) and (((old_csr_val("pmpcfg$2") ^ pmpcfg$2) >> $3 & 0xFF) == 0x00) and old_csr_val("pmpcfg$2") != 0: 0 
+    (pmpcfg{{0 ... 15} >> 2} >> {0, 8, 16, 24}{[$1%4]} & 0x80 == 0x80) and (old_csr_val("pmpaddr$1") == (pmpaddr$1)) and (pmpcfg$2 != 0): 0
 
 #This coverpoint checks the coverage of pmp-CSR-access.cgf (PMP CSRs accesses in different modes)
 #Checks pmpcgf and pmpaddr are only accessible in M mode and gets fault in S and U mode when accessed.
@@ -19,9 +19,9 @@ PMP_access_permission:
     "{csrrs, csrrw}" : 0
   csr_comb:
     #Check successful update for pmpcfg in M Mode
-    mode == 'M' and ((old("pmpcfg{0 ... 3}")    != (pmpcfg$1))    and pmpcfg$1 != 0x0): 0            
+    mode == 'M' and ((old_csr_val("pmpcfg{0 ... 3}")    != (pmpcfg$1))    and pmpcfg$1 != 0x0): 0            
     #Check successful update for pmpaddr in M Mode
-    mode == 'M' and ((old("pmpaddr{0 ... 15}")  != (pmpaddr$1))   and pmpaddr$1 != 0x0): 0        #pmpaddr successfully updated in M mode
+    mode == 'M' and ((old_csr_val("pmpaddr{0 ... 15}")  != (pmpaddr$1))   and pmpaddr$1 != 0x0): 0        #pmpaddr successfully updated in M mode
     #Check for fault for pmpcfg, pmpaddr in S, U Mode
     mode == {'S', 'U'} and mcause == ${CAUSE_ILLEGAL_INSTRUCTION}: 0 #check for illegal instruction fault
 

coverage/pmp/rv64_pmp.cgf

@@ -210,8 +210,8 @@ PMP_access_permission:
     "{csrrs, csrrw}" : 0
   csr_comb:
     #Check successful update for pmpcfg in M Mode
-    mode == 'M' and (((old("pmpcfg{0 , 2}") ^ (pmpcfg$1)) != 0x00) and pmpcfg$1 != 0x0): 0              #pmpcfg successfully updated in M mode
+    mode == 'M' and (((old_csr_val("pmpcfg{0 , 2}") ^ (pmpcfg$1)) != 0x00) and pmpcfg$1 != 0x0): 0              #pmpcfg successfully updated in M mode
     #Check successful update for pmpaddr in M Mode
-    mode == 'M' and (((old("pmpaddr{0 ... 15}") ^ (pmpaddr$1)) != 0x00) and pmpaddr$1 != 0x0): 0        #pmpaddr successfully updated in M mode
+    mode == 'M' and (((old_csr_val("pmpaddr{0 ... 15}") ^ (pmpaddr$1)) != 0x00) and pmpaddr$1 != 0x0): 0        #pmpaddr successfully updated in M mode
     #Check for fault for pmpcfg, pmpaddr in S, U Mode
     mode == {'S', 'U'} and mcause == ${CAUSE_ILLEGAL_INSTRUCTION}: 0 #check for illegal instruction fault