Run ruff check --fix

trdthg · trdthg · commit 03906c52ccce · 2024-10-18T10:34:09.000+08:00
diff --git a/riscof-plugins/rv32/makeplugin/riscof_makeplugin.py b/riscof-plugins/rv32/makeplugin/riscof_makeplugin.py
@@ -1,17 +1,10 @@
 import os
 import re
-import shutil
-import subprocess
-import shlex
 import logging
-import random
-import string
 from string import Template
 
 import riscof.utils as utils
 from riscof.pluginTemplate import pluginTemplate
-import riscof.constants as constants
-from riscv_isac.isac import isac
 
 logger = logging.getLogger()
 
diff --git a/riscof-plugins/rv32/sail_cSim/riscof_sail_cSim.py b/riscof-plugins/rv32/sail_cSim/riscof_sail_cSim.py
@@ -1,18 +1,10 @@
 import os
-import re
 import shutil
-import subprocess
-import shlex
 import logging
-import random
-import string
-from string import Template
 import distutils
 
 import riscof.utils as utils
 from riscof.pluginTemplate import pluginTemplate
-import riscof.constants as constants
-from riscv_isac.isac import isac
 
 logger = logging.getLogger()
 
diff --git a/riscof-plugins/rv32/spike_simple/riscof_spike_simple.py b/riscof-plugins/rv32/spike_simple/riscof_spike_simple.py
@@ -1,16 +1,7 @@
 import os
-import re
-import shutil
-import subprocess
-import shlex
 import logging
-import random
-import string
-from string import Template
-import sys
 
 import riscof.utils as utils
-import riscof.constants as constants
 from riscof.pluginTemplate import pluginTemplate
 
 logger = logging.getLogger()
diff --git a/riscof-plugins/rv64/makeplugin/riscof_makeplugin.py b/riscof-plugins/rv64/makeplugin/riscof_makeplugin.py
@@ -1,17 +1,10 @@
 import os
 import re
-import shutil
-import subprocess
-import shlex
 import logging
-import random
-import string
 from string import Template
 
 import riscof.utils as utils
 from riscof.pluginTemplate import pluginTemplate
-import riscof.constants as constants
-from riscv_isac.isac import isac
 
 logger = logging.getLogger()
 
diff --git a/riscof-plugins/rv64/sail_cSim/riscof_sail_cSim.py b/riscof-plugins/rv64/sail_cSim/riscof_sail_cSim.py
@@ -1,17 +1,9 @@
 import os
-import re
 import shutil
-import subprocess
-import shlex
 import logging
-import random
-import string
-from string import Template
 
 import riscof.utils as utils
 from riscof.pluginTemplate import pluginTemplate
-import riscof.constants as constants
-from riscv_isac.isac import isac
 
 logger = logging.getLogger()
 
diff --git a/riscof-plugins/rv64/spike_simple/riscof_spike_simple.py b/riscof-plugins/rv64/spike_simple/riscof_spike_simple.py
@@ -1,16 +1,7 @@
 import os
-import re
-import shutil
-import subprocess
-import shlex
 import logging
-import random
-import string
-from string import Template
-import sys
 
 import riscof.utils as utils
-import riscof.constants as constants
 from riscof.pluginTemplate import pluginTemplate
 
 logger = logging.getLogger()
diff --git a/riscv-ctg/docs/source/conf.py b/riscv-ctg/docs/source/conf.py
@@ -15,7 +15,6 @@
 
 import sys
 import os
-import shlex
 import re
 
 def get_version():
diff --git a/riscv-ctg/docs/sphinxext/cairosvgconverter.py b/riscv-ctg/docs/sphinxext/cairosvgconverter.py
@@ -1,11 +1,8 @@
 # -*- coding: utf-8 -*-
 """
 """
-from sphinx.errors import ExtensionError
-from sphinx.locale import _
 from sphinx.transforms.post_transforms.images import ImageConverter
 from sphinx.util import logging
-from sphinx.util.osutil import ENOENT, EPIPE, EINVAL
 from cairosvg import svg2pdf
 
 logger = logging.getLogger(__name__)
diff --git a/riscv-ctg/riscv_ctg/cross_comb.py b/riscv-ctg/riscv_ctg/cross_comb.py
@@ -3,13 +3,11 @@
 from constraint import *
 
 import riscv_isac.utils as isac_utils
-from riscv_ctg import constants
 
 import riscv_ctg.utils as utils
 import riscv_ctg.constants as const
 from riscv_ctg.constants import *
 from riscv_ctg.log import logger
-from riscv_ctg.__init__ import __version__
 from riscv_ctg.generator import OPS
 from riscv_ctg.dsp_function import *
 
diff --git a/riscv-ctg/riscv_ctg/csr_comb.py b/riscv-ctg/riscv_ctg/csr_comb.py
@@ -300,7 +300,7 @@ def csr_comb(self, cgf_node):
                             logger.error(f'Skipping invalid csr_comb solution with modifiers on more than one registers for the coverpoint: {covpt}')
                             continue
 
-                    if not csr_reg in reg_mask_val_mod_dict:
+                    if csr_reg not in reg_mask_val_mod_dict:
                         if mod == 'old':
                             reg_mask_val_mod_dict[csr_reg] = [0, 0, 0, 0, mask, val]
                         elif mod == 'write':
diff --git a/riscv-ctg/riscv_ctg/ctg.py b/riscv-ctg/riscv_ctg/ctg.py
@@ -1,7 +1,7 @@
 # See LICENSE.incore file for details
 
 import copy
-import os,re
+import os
 import multiprocessing as mp
 
 import time
diff --git a/riscv-ctg/riscv_ctg/dsp_function.py b/riscv-ctg/riscv_ctg/dsp_function.py
@@ -27,13 +27,13 @@ def simd_val_vars(operand, xlen, bit_width):
 
 def get_fmt_sz(bit_width):
     if bit_width == 8:
-        fmt = f"#02x"
+        fmt = "#02x"
     elif bit_width == 16:
-        fmt = f"#04x"
+        fmt = "#04x"
     elif bit_width == 32:
-        fmt = f"#08x"
+        fmt = "#08x"
     else:
-        fmt = f"#016x"
+        fmt = "#016x"
     if bit_width == 8:
         sz = "b"
     elif bit_width == 16:
@@ -55,13 +55,13 @@ def gen_fmt(bit_width):
     '''
 
     if bit_width == 8:
-        fmt = f"#02x"
+        fmt = "#02x"
     elif bit_width == 16:
-        fmt = f"#04x"
+        fmt = "#04x"
     elif bit_width == 32:
-        fmt = f"#08x"
+        fmt = "#08x"
     else:
-        fmt = f"#016x"
+        fmt = "#016x"
     return fmt
 
 def gen_sz(bit_width):
@@ -111,7 +111,7 @@ def concat_simd_data(instr_dict, xlen, _bit_width):
                 rs1_val = int(instr['rs1_val'])
                 if rs1_val < 0:
                     rs1_val = rs1_val + twocompl_offset
-                instr['rs1_val'] = format(rs1_val, f"#0x")
+                instr['rs1_val'] = format(rs1_val, "#0x")
             else:   # concatenates all element of a SIMD register into a single value
                 rs1_val = 0
                 for i in range(xlen//bit_width1):
@@ -131,7 +131,7 @@ def concat_simd_data(instr_dict, xlen, _bit_width):
                 rs2_val = int(instr['rs2_val'])
                 if rs2_val < 0:
                     rs2_val = rs2_val + twocompl_offset
-                instr['rs2_val'] = format(rs2_val, f"#0x")
+                instr['rs2_val'] = format(rs2_val, "#0x")
             else:   # concatenates all element of a SIMD register into a single value
                 rs2_val = 0
                 for i in range(xlen//bit_width2):
@@ -143,7 +143,7 @@ def concat_simd_data(instr_dict, xlen, _bit_width):
                 instr['rs2_val'] = format(rs2_val, f"#0{xlen//4}x")
         if 'imm_val' in instr:
             imm_val = int(instr['imm_val'])
-            instr['imm_val'] = format(imm_val, f"#0x")
+            instr['imm_val'] = format(imm_val, "#0x")
 
 def incr_reg_num(reg):
     name = reg[0]
@@ -208,7 +208,7 @@ def gen_pair_reg_data(instr_dict, xlen, _bit_width, p64_profile):
             else:
                 instr['rs1_val'] = format(rs1_val, f"#0{2+xlen//4}x")
             if rs1_width == 64 and (len(p64_profile) >= 3):
-                instr['rs1_val64'] = format(rs1_val, f"#018x")
+                instr['rs1_val64'] = format(rs1_val, "#018x")
 
         if 'rs2' in instr:
             twocompl_offset = 1<<bit_width2
@@ -233,11 +233,11 @@ def gen_pair_reg_data(instr_dict, xlen, _bit_width, p64_profile):
             else:
                 instr['rs2_val'] = format(rs2_val, f"#0{2+xlen//4}x")
             if rs2_width == 64 and (len(p64_profile) >= 3):
-                instr['rs2_val64'] = format(rs2_val, f"#018x")
+                instr['rs2_val64'] = format(rs2_val, "#018x")
 
         if 'rd' in instr and rd_width > xlen:
             instr['rd_hi'] = incr_reg_num(instr['rd'])
 
         if 'imm_val' in instr:
             imm_val = int(instr['imm_val'])
-            instr['imm_val'] = format(imm_val, f"#0x")
+            instr['imm_val'] = format(imm_val, "#0x")
diff --git a/riscv-ctg/riscv_ctg/generator.py b/riscv-ctg/riscv_ctg/generator.py
@@ -1,18 +1,15 @@
 # See LICENSE.incore for details
-import random
 from collections import defaultdict
 from constraint import *
 import re
 from riscv_ctg.constants import *
 from riscv_ctg.log import logger
 from riscv_ctg.helpers import *
 from riscv_isac.InstructionObject import instructionObject
-import time
 from math import *
 import struct
 import sys
 import itertools
-import re
 
 # F
 one_operand_finstructions = ["fsqrt.s","fmv.x.w","fcvt.wu.s","fcvt.w.s","fclass.s","fcvt.l.s","fcvt.lu.s","fcvt.s.l","fcvt.s.lu"]
diff --git a/riscv-ctg/riscv_ctg/main.py b/riscv-ctg/riscv_ctg/main.py
@@ -1,13 +1,11 @@
 # See LICENSE.incore for details
 """Console script for riscv_ctg."""
 
-import click,os
+import click
+import os
 
-from riscv_ctg.log import logger
 from riscv_ctg.ctg import ctg
 from riscv_ctg.__init__ import __version__
-from riscv_ctg.constants import env,gen_sign_dataset,gen_usign_dataset
-from riscv_isac.cgf_normalize import expand_cgf
 @click.command()
 @click.version_option(prog_name="RISC-V Compliance Test Generator",version=__version__)
 @click.option('--verbose', '-v', default='error', help='Set verbose level', type=click.Choice(['info','error','debug','warning'],case_sensitive=False))
diff --git a/riscv-ctg/riscv_ctg/utils.py b/riscv-ctg/riscv_ctg/utils.py
@@ -1,7 +1,6 @@
 # See LICENSE.incore for details
 
 """Common Utils """
-import sys
 import os
 import subprocess
 import shlex
@@ -210,7 +209,7 @@ def run(self, **kwargs):
         """
         kwargs.setdefault('shell', self._is_shell_command())
         cwd = self._path2str(kwargs.get(
-            'cwd')) if not kwargs.get('cwd') is None else self._path2str(
+            'cwd')) if kwargs.get('cwd') is not None else self._path2str(
                 os.getcwd())
         kwargs.update({'cwd': cwd})
         logger.debug(cwd)
diff --git a/riscv-ctg/tests/test_riscv_ctg.py b/riscv-ctg/tests/test_riscv_ctg.py
@@ -1,7 +1,6 @@
 # See Licence.incore for details.
 from click.testing import CliRunner
 from riscv_ctg.main import cli
-from riscv_ctg.ctg import ctg
 import pytest
 
 @pytest.fixture
diff --git a/riscv-isac/docs/source/conf.py b/riscv-isac/docs/source/conf.py
@@ -15,7 +15,6 @@
 
 import sys
 import os
-import shlex
 import re
 
 def get_version():
diff --git a/riscv-isac/docs/sphinxext/cairosvgconverter.py b/riscv-isac/docs/sphinxext/cairosvgconverter.py
@@ -1,11 +1,8 @@
 # -*- coding: utf-8 -*-
 """
 """
-from sphinx.errors import ExtensionError
-from sphinx.locale import _
 from sphinx.transforms.post_transforms.images import ImageConverter
 from sphinx.util import logging
-from sphinx.util.osutil import ENOENT, EPIPE, EINVAL
 from cairosvg import svg2pdf
 
 logger = logging.getLogger(__name__)
diff --git a/riscv-isac/interface.py b/riscv-isac/interface.py
@@ -1,7 +1,6 @@
 import importlib
 import pluggy
 from riscv_isac.plugins.specification import *
-import riscv_isac.plugins as plugins
 
 
 def interface (trace, arch, mode):
diff --git a/riscv-isac/riscv_isac/InstructionObject.py b/riscv-isac/riscv_isac/InstructionObject.py
@@ -521,11 +521,11 @@ def evaluate_rs1_val_p_ext(self, instr_vars, arch_state):
         return self.evaluate_reg_val_p_ext(self.rs1[0], self.rs1_nregs, arch_state)
 
    
-    @evaluator_func("rs1_val", lambda **params: not params['instr_name'] in unsgn_rs1 and not params['is_rvp'] and params['rs1'] is not None and params['rs1'][1] == 'x' and not params['inxFlag'])
+    @evaluator_func("rs1_val", lambda **params: params['instr_name'] not in unsgn_rs1 and not params['is_rvp'] and params['rs1'] is not None and params['rs1'][1] == 'x' and not params['inxFlag'])
     def evaluate_rs1_val_sgn(self, instr_vars, arch_state):
         return self.evaluate_reg_val_sgn(self.rs1[0], instr_vars['xlen'], arch_state)
 
-    @evaluator_func("rs1_val", lambda **params: not params['instr_name'] in unsgn_rs1 and not params['is_rvp'] and params['rs1'] is not None and (params['rs1'][1] == 'f' or params['inxFlag']))
+    @evaluator_func("rs1_val", lambda **params: params['instr_name'] not in unsgn_rs1 and not params['is_rvp'] and params['rs1'] is not None and (params['rs1'][1] == 'f' or params['inxFlag']))
     def evaluate_rs1_val_fsgn(self, instr_vars, arch_state):
         return self.evaluate_reg_val_fsgn(self.rs1[0], instr_vars['flen'], instr_vars['xlen'],arch_state)
    
@@ -546,12 +546,12 @@ def evaluate_rs2_val_p_ext(self, instr_vars, arch_state):
         return self.evaluate_reg_val_p_ext(self.rs2[0], self.rs2_nregs, arch_state)
 
 
-    @evaluator_func("rs2_val", lambda **params: not params['instr_name'] in unsgn_rs2 and not params['is_rvp'] and params['rs2'] is not None and params['rs2'][1] == 'x'  and not params['inxFlag'])
+    @evaluator_func("rs2_val", lambda **params: params['instr_name'] not in unsgn_rs2 and not params['is_rvp'] and params['rs2'] is not None and params['rs2'][1] == 'x'  and not params['inxFlag'])
     def evaluate_rs2_val_sgn(self, instr_vars, arch_state):
         return self.evaluate_reg_val_sgn(self.rs2[0], instr_vars['xlen'], arch_state)
 
 
-    @evaluator_func("rs2_val", lambda **params: not params['instr_name'] in unsgn_rs2 and not params['is_rvp'] and params['rs2'] is not None and (params['rs2'][1] == 'f' or params['inxFlag']))
+    @evaluator_func("rs2_val", lambda **params: params['instr_name'] not in unsgn_rs2 and not params['is_rvp'] and params['rs2'] is not None and (params['rs2'][1] == 'f' or params['inxFlag']))
     def evaluate_rs2_val_fsgn(self, instr_vars, arch_state):
         return self.evaluate_reg_val_fsgn(self.rs2[0], instr_vars['flen'], instr_vars['xlen'], arch_state)
 
@@ -579,7 +579,7 @@ def evaluate_rs3_val_fsgn(self, instr_vars, arch_state):
     def evaluate_rd_val_unsgn(self, instr_vars, arch_state):
         return self.evaluate_reg_val_unsgn(self.rd[0], instr_vars['xlen'], arch_state)
 
-    @evaluator_func("rd_val", lambda **params: not params['instr_name'] in unsgn_rd and params['rd'] is not None  and params['rd'][1] == 'x')
+    @evaluator_func("rd_val", lambda **params: params['instr_name'] not in unsgn_rd and params['rd'] is not None  and params['rd'][1] == 'x')
     def evaluate_rd_val_sgn(self, instr_vars, arch_state):
         return self.evaluate_reg_val_sgn(self.rd[0], instr_vars['xlen'], arch_state)
 
diff --git a/riscv-isac/riscv_isac/cgf_normalize.py b/riscv-isac/riscv_isac/cgf_normalize.py
@@ -1,13 +1,10 @@
 # See LICENSE.incore for details
 from math import *
-import pprint
 import riscv_isac.utils as utils
 import itertools
 import random
-import copy
 from riscv_isac.fp_dataset import *
 
-import time
 
 def twos(val,bits):
     '''
diff --git a/riscv-isac/riscv_isac/coverage.py b/riscv-isac/riscv_isac/coverage.py
diff --git a/riscv-isac/riscv_isac/data/rvopcodesdecoder.py b/riscv-isac/riscv_isac/data/rvopcodesdecoder.py
diff --git a/riscv-isac/riscv_isac/isac.py b/riscv-isac/riscv_isac/isac.py
diff --git a/riscv-isac/riscv_isac/plugins/internaldecoder.py b/riscv-isac/riscv_isac/plugins/internaldecoder.py
diff --git a/riscv-isac/riscv_isac/plugins/translator_cgf.py b/riscv-isac/riscv_isac/plugins/translator_cgf.py
diff --git a/riscv-isac/riscv_isac/utils.py b/riscv-isac/riscv_isac/utils.py
