Merge pull request #28 from riscv-non-isa/Issue-17

Fixed spelling - Issue 17

Author: IainCRobertson

src/hti.adoc

@@ -55,7 +55,7 @@ target that _can_ be inferred from the source code.
 * If context or time is supported then the _instruction_address_ for:
 ** The last instruction retired before a context or a time change;
 ** The first instruction retired following a context or time change.
-* Whether jump targets are sequentially inferable or not.
+* Whether jump targets are sequentially inferrable or not.
 
 The mandatory information is the bare-minimum required to implement a basic
 branch trace encoding algorithm.
@@ -70,39 +70,39 @@ be inferred or not;
 encoder efficiency, particularly for loops. This requires
 the encoder to be aware of the address of all branches, whether they are
 taken or not.
-* Uninferable jumps can be treated as inferable (which don't need to be
+* Uninferrable jumps can be treated as inferrable (which don't need to be
 reported in the trace output) if both the jump and the preceding
 instruction which loads the target into a register have been traced.
 
 [[JumpClasses]]
 ==== Jump classification and target inference
 
-Jumps are classified as _inferable_, or _uninferable_. An _inferable_
+Jumps are classified as _inferrable_, or _uninferrable_. An _inferrable_
 jump has a target which can be deduced from the binary executable or
 representation thereof (e.g. ELF). For the purposes of this
 specification, the following strict definition applies:
 
 If the target of a jump is supplied via a constant embedded within the
-jump opcode, it is classified as _inferable_. Jumps which are not
-_inferable_ are by definition _uninferable_.
+jump opcode, it is classified as _inferrable_. Jumps which are not
+_inferrable_ are by definition _uninferrable_.
 
 However, there are some jump targets which can still be deduced from the
 binary executable by considering pairs of instructions even though by
-the above definition they are classified as uninferable. Specifically,
+the above definition they are classified as uninferrable. Specifically,
 when the source register for the jump instruction is supplied via
 
 * an *_lui_* or *_c.lui_* (a register which contains a constant), or
 * an *_auipc_* (a register which contains a constant offset from the
 PC).
 
-Such jump targets are classified as _sequentially inferable_ if the pair
+Such jump targets are classified as _sequentially inferrable_ if the pair
 of instructions are retired consecutively (i.e. the *_auipc_*, *_lui_*
 or *_c.lui_* immediately precedes the jump). Note: the restriction that
 the instructions are retired consecutively is necessary in order to
 minimize the additional signalling needed between the hart and the
 encoder, and should have a minimal impact on trace efficiency as it is
 anticipated that consecutive execution will be the norm. Support for
-sequentially inferable jumps is optional.
+sequentially inferrable jumps is optional.
 
 Jumps may optionally be further classified according to the recommended calling convention into _Calls_, _Returns_, _Co-routine swap_, and _other jumps with and without linkage_.  Full details are provided in <<tab:itype4>>.
 
@@ -183,8 +183,8 @@ retired on this cycle.
 Encoding given in Table <<tab:context-type>>. Codes 2-3
 optional.
 |*sijump* | OR | If *itype* indicates that this block ends with an
-uninferable discontinuity, setting this signal to 1 indicates that it is
-sequentially inferable and may be treated as inferable by the encoder if
+uninferrable discontinuity, setting this signal to 1 indicates that it is
+sequentially inferrable and may be treated as inferrable by the encoder if
 the preceding *_auipc_*, *_lui_* or *_c.lui_* has been traced. Ignored
 for *itype* codes other than 6, 8, 10, 12 or 14.
 |===
@@ -234,7 +234,7 @@ retired instruction
 |5 | Taken branch |  <<itype_branch,Conditional branch>> | Taken direct, conditional branch
 |6 | Uninferrable jump +
      Pop/Return | JALR rd, rs +
-                  CM.POPRET| Uninferable jump +
+                  CM.POPRET| Uninferrable jump +
                   Defined by *Zcmt* extension
 |7 | reserved | |
 |===
@@ -255,7 +255,7 @@ retired instruction
 |5 | Taken branch |  <<itype_branch,Conditional branch>> | Taken direct, conditional branch
 | 6 +
  7 | reserved | |
-|8 | Uninferable call | JALR rd, rs +
+|8 | Uninferrable call | JALR rd, rs +
                                     +
                         C.JALR rs | rd = `link` and rs != `link` +
                                     rd = `link` and rs = `link` and rd = rs +
@@ -265,7 +265,7 @@ retired instruction
                        CM.JALT| rd = `link` +
                                 Expands to `JAL x1, offset` +
                                 Defined by <<zcmt,Zcmt>> extension
-|10 | Uninferable jump +
+|10 | Uninferrable jump +
       (without linkage) | JALR rd, rs +
                           C.JR rs    | rd = *x0* and rs != `link` +
                                        rs != `link` +
@@ -283,8 +283,8 @@ retired instruction
                    CM.POPRET| rd != `link` and rs = `link` +
                               rs = `link` +
                               Defined by *Zcmt* extension
-|14 | Other uninferable jump (with linkage) | JALR rd, rs | rd != `link` and rd != *x0* and rs != `link` +
-|15 | Other inferable jump (without linkage) | JAL rd | rd != `link` and rd != *x0*
+|14 | Other uninferrable jump (with linkage) | JALR rd, rs | rd != `link` and rd != *x0* and rs != `link` +
+|15 | Other inferrable jump (without linkage) | JAL rd | rd != `link` and rd != *x0*
 |===
 
 
@@ -295,7 +295,7 @@ NOTE: Branches (*itype*=4, 5) are always conditional, direct branches. In RISC-V
 NOTE: Symbol `link` means register *x1* or *x5* as specified in *The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA* document.
 
 [[zcmt]]
-NOTE: Jump instructions (CM.JT and CM.JALT) defined by ratified *Zcmt* extension are handled as direct (inferable) jumps as jump tables are assumed to be static and known to the decoder.
+NOTE: Jump instructions (CM.JT and CM.JALT) defined by ratified *Zcmt* extension are handled as direct (inferrable) jumps as jump tables are assumed to be static and known to the decoder.
 
 <<<
 
@@ -329,7 +329,7 @@ block without having access to the size of every instruction in the
 block.
 
 *itype* can be 3 or 4 bits wide. If _itype_width_p_ is 3, a single code
-(6) is used to indicate all uninferable jumps. This is simpler to
+(6) is used to indicate all uninferrable jumps. This is simpler to
 implement, but precludes use of the implicit return mode (see
 <<impret,Implicit Return>>), which requires jump types to be fully classified.
 Note that when _itype_width_p_ is 3, *itype* = 0 is used for inferrable calls.
@@ -356,11 +356,11 @@ instructions up to the 1st branch must be reported in group 0 and
 instructions up to the 2nd branch must be reported in group 1 and so on.
 
 *sijump* is optional and may be omitted if the hart does not implement
-the logic to detect sequentially inferable jumps. If the encoder offers
+the logic to detect sequentially inferrable jumps. If the encoder offers
 an *sijump* input it must also provide a parameter to indicate whether
 the input is connected to a hart that implements this capability, or
 tied off. This is to ensure the decoder can be made aware of the hart’s
-capability. Enabling sequentially inferable jump mode in the encoder and
+capability. Enabling sequentially inferrable jump mode in the encoder and
 decoder when the hart does not support it will prevent correct
 reconstruction by the decoder.