Merge pull request #847 from Silabs-ArjanB/ArjanB_nos1

Signal rename

Author: silabs-oysteink

rtl/cv32e40x_controller_bypass.sv

@@ -147,9 +147,9 @@ module cv32e40x_controller_bypass import cv32e40x_pkg::*;
                               (ex_wb_pipe_i.instr_valid && (ex_wb_pipe_i.csr_en || (ex_wb_pipe_i.sys_en && ex_wb_pipe_i.sys_mret_insn) || ex_wb_pipe_i.instr_meta.clic_ptr || ex_wb_pipe_i.instr_meta.mret_ptr))
                               );
 
-  // Stall ID when WFI or WFE is active in EX.
-  // Prevent load/store following a WFI or WFE in the pipeline
-  assign ctrl_byp_o.wfi_wfe_stall = (id_ex_pipe_i.sys_en && (id_ex_pipe_i.sys_wfi_insn || id_ex_pipe_i.sys_wfe_insn) && id_ex_pipe_i.instr_valid);
+  // Stall ID when instruction that can trigger sleep (e.g. WFI or WFE) is active in EX.
+  // Prevent load/store following a sleep instruction in the pipeline
+  assign ctrl_byp_o.sleep_stall = (id_ex_pipe_i.sys_en && (id_ex_pipe_i.sys_wfi_insn || id_ex_pipe_i.sys_wfe_insn) && id_ex_pipe_i.instr_valid);
 
   // Stall ID when mnxti CSR is accessed in EX
   // This is needed because the data bypass from EX uses csr_rdata, and for mnxti this is actually mstatus and not the result

rtl/cv32e40x_controller_fsm.sv

@@ -21,7 +21,7 @@
 //                                                                            //
 // Additional contributions by:                                               //
 //                                                                            //
-// Design Name:    cv32e40x_controller_fsm                                 //
+// Design Name:    cv32e40x_controller_fsm                                    //
 // Project Name:   CV32E40X                                                   //
 // Language:       SystemVerilog                                              //
 //                                                                            //
@@ -651,7 +651,7 @@ module cv32e40x_controller_fsm import cv32e40x_pkg::*;
     //   - If not checking for id_stage_haltable for interrupts and debug, the core could end up in a situation where it tries to create a bubble
     //     by halting ID, but the condition disallowing interrupt or debug will not disappear until the sequence currently handled by the ID stage
     //     is done. This would create an unrecoverable deadlock.
-    ctrl_fsm_o.halt_id          = (ctrl_byp_i.jalr_stall || ctrl_byp_i.load_stall || ctrl_byp_i.csr_stall || ctrl_byp_i.wfi_wfe_stall || ctrl_byp_i.mnxti_id_stall) ||
+    ctrl_fsm_o.halt_id          = (ctrl_byp_i.jalr_stall || ctrl_byp_i.load_stall || ctrl_byp_i.csr_stall || ctrl_byp_i.sleep_stall || ctrl_byp_i.mnxti_id_stall) ||
                                   ((pending_interrupt || pending_nmi || pending_nmi_early) && debug_interruptible && id_stage_haltable)                             ||
                                   ((pending_async_debug || pending_sync_debug) && id_stage_haltable);
 

rtl/include/cv32e40x_pkg.sv

@@ -1309,7 +1309,7 @@ typedef struct packed {
   logic         jalr_stall;             // Stall due to JALR hazard (JALR used result from EX or LSU result in WB)
   logic         load_stall;             // Stall due to load operation
   logic         csr_stall;
-  logic         wfi_wfe_stall;
+  logic         sleep_stall;            // Stall ID due to sleep (e.g. WFI, WFE) instruction in EX
   logic         mnxti_id_stall;         // Stall ID due to mnxti CSR access in EX
   logic         mnxti_ex_stall;         // Stall EX due to LSU instruction in WB
   logic         minstret_stall;         // Stall due to minstret/h read in EX